United Integrated Circuits Corp.

Michael Lee

A DRAM capacitor. A first dielectric layer is formed over a substrate having a gate and source/drain regions, and a plug penetrating through the first dielectric layer to couple with the source/drain regions. A bottom electrode comprising a vertical pole, a metal plate, a first spacer and a second spacer is formed and contacts with the plug. A second dielectric layer is formed on the bottom electrode, and then a conductive layer is formed on the second dielectric layer.

Capacitor in a dynamic random access memory

A method for forming a bottom electrode of a capacitor is provided. A substrate having a conductive region is provided. A first insulation layer, a stop layer and a second insulation layer are formed on the substrate in order. The first insulation layer, the stop layer and the second insulation layer are patterned to form an opening. The opening exposes the conductive region in the substrate. A first conductive layer is formed on the second insulation layer and fills the opening, and then the first conductive layer is defined to form a plug and a metal plate. The plug can be electrically connected with the conductive region. The metal plate is used as a mask, and the second insulation layer is removed by anisotropic etching to form a third insulation layer having a first distance from the third insulation layer surface to the stop layer surface. Then, the third insulation layer is removed by isotropic etching to form a fourth insulation layer having a second distance from the fourth insulation layer surface to the stop layer surface. A second conductive layer is formed on the fourth insulation layer and the metal plate. Finally, the second conductive layer is removed by anisotropic etching to expose the metal plate and a portion of the fourth insulation layer. Then, the fourth insulation layer is removed by isotropic etching to expose the stop layer and the plug.

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Ta-Li, Taiwan

Michael Lee