Synopsys, Inc.

Etec Systems, Inc.

Michael Lawrence Rieger

Daniel D Hung

Michael G Brashler

Thomas Brett Hall

Mathias Boman

Naji V Bekhazi

Thomas Christopher Cecil

Benjamin David Painter

Micheal D Cranford

John P Stirniman

Victor Moroz

Michel Luc Cote

Philippe Hurat

Robert M Lugg

Jeff Mayhew

Timothy N Thomas

Paul C Allen

Robin Lynn Teitzel

Matthew J Jolley

Michael Bohan

A method of encoding a stream of data bits includes encoding a bitof the data stream as a first symbol if a bit immediately preceding the bitis encoded as 0 and a bit of the data stream immediately succeeding the bitis 0, encoding the bit immediately succeeding the bitas 1, encoding a bitof the data stream as a second symbol if a bit immediately preceding the bitis encoded as 1 and a bit of the data stream immediately succeeding the bitis 1, and encoding the bit immediately succeeding the bitas 0.

Phase-shifting encoding for signal transition minimization

A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure 'shots' are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Sub-resolution assist feature implementation for shot generation

Sub-resolution assist feature implementation with shot optimization

Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.

Self-aligned via interconnect using relaxed patterning exposure

Sub-resolution assist feature implementation using shot optimization

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.

Incremental concurrent processing for efficient computation of high-volume layout data

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Flash-based anti-aliasing techniques for high-accuracy high-efficiency mask synthesis

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value) with a new layer, or alternatively using a conventional layer (e.g. metal) with a new datatype (e.g. value), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Silicon tolerance specification using shapes as design intent markers

An embodiment of the present invention provides a system that computes the effect of perturbations to a pattern layout during an OPC process. During operation, the system receives a pattern layout and a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. The system additionally receives a perturbation pattern to be added onto the pattern layout. Next, for a query location on the pattern layout, the system obtains a set of convolution values at the query location by using model flash lookup tables to convolve the perturbation pattern with the set of lithography model kernels. The system then updates the set of convolved patterns at the query location to account for the effect of the perturbation pattern by combining the set of convolution values with the set of convolved patterns.

Flash-based updating techniques for high-accuracy high efficiency mask synthesis

One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Flash-based anti-aliasing techniques for high-accuracy high efficiency mask synthesis

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value 0) with a new layer, or alternatively using a conventional layer (e.g. metal 3) with a new datatype (e.g. value 1), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

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Skamania, WA, United States of America

Michael Lawrence Rieger