International Business Machines Corporation

Globalfoundries Inc.

Michael Lawrence Gautsch

Natalie Barbara Feilchenfeld

Zhong-Xiang He

Douglas Duane Coolbaugh

James Albert Slinkman

Ebenezer E Eshun

Vidhya Ramachandran

Matthew D Moon

Barbara Ann Waterhouse

Jeffrey P Gambino

Mark David Jaffe

Alvin Jose Joseph

Robert Mark Rassel

Xuefeng Liu

Alan Bernard Botula

Randy Lee Wolf

Max Gerald Levy

Stephen Arthur St Onge

David S Collins

Bradley Alan Orner

Robert L Barry

Phillip Francis Chapman

Kevin N Ogg

Frederick Gustav Anderson

John J Benoit

Jiansheng Xu

Jean-Marc Petillat

Philippe Ramos

Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist. Simulations are subsequently performed using this netlist to generate a performance model for the IC.

Integrated circuit performance modeling that includes substrate-generated signal distortions

Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

Segmented guard ring structures with electrically insulated gap structures and design structures thereof

A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

Optimized device isolation

An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

Trench forming method and structure

Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask

Growing community of inventors

Jericho, VT, United States of America

Michael Lawrence Gautsch