International Business Machines Corporation

Michael Launsbach

Todd Alan Christensen

Travis Reynold Hebig

Derick Gardner Behrends

Daniel Mark Nelson

John Edward Sheets, Ii

Igor Arsovski

Curtis Walter Preuss

David W Siljenberg

Delbert Raymond Cecchi

A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.

Level shifter for a time-varying input

A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.

Partial update in a ternary content addressable memory

A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.

Integrated decoupling capacitor utilizing through-silicon via

A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Layout to minimize FET variation in small dimension photolithography

A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.

Power management SRAM write bit line drive circuit

A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

Power management domino SRAM bit line discharge circuit

A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.

Single cycle data copy for two-port SRAM

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Data security for dynamic random access memory using body bias to clear data at power-up

A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

Implementing RC and coupling delay correction for SRAM

A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.

Implementing power saving self powering down latch structure

A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.

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Rochester, MN, United States of America

Michael Launsbach