Qualcomm Incorporated

Dialog Semiconductor (UK) Limited

Dialog Semiconductor Gmbh

Michael Laisne

Hans Martin Von Staudt

Srinivas Varadarajan

Arvid G Sammuli

Songlin Zuo

Raghunath R Bhattagiri

Xiangdong Pan

Shiqun Gu

Matthew Michael Nowak

Karim Arabi

Foua Vang

Prayag Bhanubhai Patel

Mark Eason

Martin L Villafana

Tsvetomir Petrov

Vivek Bhan

Hailong Cui

Hongjun Yao

Triphuong Nguyen

Glen T Kim

Mark C Chan

Donald D Lyons

A method of producing an apparatus comprising an electrical circuit that has one or more characteristics that meet a design specification is presented. The method includes designing the electrical circuit with a trim circuit having a trim value that is variable, The electrical circuit is adjustable based on the trim value of the trim circuit. There is encoding of the functional circuit information and/or trim circuit information in a tag, The method has a reading of the functional circuit information and/or the trim circuit information stored in the tag and the determining of the trim value for the trim circuit that results in the characteristic of the electrical circuit meeting the design specification using the functional circuit information and/or the trim circuit information.

Electrical circuit comprising a trim circuit

An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

Communication interface

An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value.

Data recirculation in configured scan paths

An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Daisy chain connection for testing continuity in a semiconductor die

A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Techniques providing fiducial markers for failure analysis

An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.

Systems and methods utilizing redundancy in semiconductor chip interconnects

Quiescent supply current (I) verification, prediction, and debugging of low power semiconductor devices are enhanced by Idefect diagnosis. If all Ipatterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually Ipatterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad Ipatterns can identify root causes of Iissues and additional constraints to fix the bad Ivectors. These verification procedures are achieving Itest success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled Itest.

[object Object]

An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Integrated circuit with improved test capability via reduced pin count

Growing community of inventors

Encinitas, CA, United States of America

Michael Laisne