Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Data General Corporation

Alliant Computer Systems Corporation

Hewlett Packard Enterprise Development LP

Intel Corporation

Institute for the Development of Emerging Architectures, L.l.c.

Michael L Ziegler

William R Bryg

Stephen G Burger

Robert J Brooks

Robert D Odineal

James B Williams

Thomas R Hotchkiss

Craig R Frink

Carol Linda Thompson

Michael B Druke

K Monroe Bridges

John L Wood

Robert L Fredieu

Gary N Hammond

Kent Andrew Dickey

Kenneth K Chan

Kenneth D Holberger

Lawrence D K B Dwyer

Brendan A Voge

Eric W Hamilton

Dale Calvin Morris

Bryan D Hornung

Heather D Achilles

James Marriot Guyer

Jerome C Huck

Steven Glen Jorgensen

Judge K Arora

Gregory S Palmer

David L Whipple

John F Shelton

Jonathan Greenlaw

Barry J Flahive

Charles J Holland

Aland B Adams

Richard W Coyle

Robert E Naas

Steven Wallach

Ward Baxter, Ii

Bernard L Stumpf

Michael K Traynor

Peter G Marshall

James E Veres

Carl J Alsing

James M Hull

Chandra R Vora

Helen Nusbaum

Joseph Hani Hassoun

Edward J Rasala

Carl Henry

Paymon Ghamami

Steven Traub

Thomas West

Bo Quan

Jeff Kurtze

John R Van Roekel

Steve Hamilton

Scott Greenidge

Mark Bagula

Jonathan S Blau

Ruby B L Lee

A credit-based method for controlling data communications in a computer system between a sender and a receiver coupled by an ordered communication link is described herein. A request for a credit check is transmitted from the sender to the receiver via the ordered communication link. An initial number of credits are allocated to the sender in a credit counter. A snapshot counter is set to a value of the credit counter and us updated as returned credits are received. A number of reported credits are determined based on a credit check response message received from the receiver. The returned credits are ordered relative to the credit check response message. The number of credits is checked for consistency based on a number of the snapshot counter and the number of reported credits.

Consistency checking for credit-based control of data communications

Techniques are provided to trace packet descriptors. A received packet may be identified. A packet descriptor associated with the received packet may be created. A trace indicator in the packet descriptor may be set. The presence of a packet descriptor with the trace indicator set may be logged by a detector.

Packet descriptor trace indicators

Techniques are provided for sending request messages to destination nodes. Destination nodes may be indicated as unresolved. Request messages are sent to destination nodes indicated as unresolved.

Sending request messages to nodes indicated as unresolved

Techniques are provided for performing a delay. A request for a delay may be received. A plurality of delay queues may be provided, with each delay queue spanning a range of delay remaining. The request may be assigned to a delay queue based on the delay remaining. The request may be moved to a different delay queue as the delay remaining decreases.

Delay queues based on delay remaining

Techniques for using target issue intervals are provided. Request messages may identify the size of a data packet. A target issue interval may be determined based on the request messages. The target issue interval may be used to insert a delay between sending subsequent request messages.

Target issue intervals

Techniques for delays based on packet sizes are provided. Request messages may identify the size of a data packet. Delays may be initiated based in part on a portion of the size of the data packet. The delays may also be based in part on target issue intervals. Request messages may be sent after the delays.

Delays based on packet sizes

Techniques described herein provide for sending data packets from source to destination nodes. Indicators, such as counters, may determine the configuration of node interfaces. The data packets may be sent based on a comparison of current and stored indicators.

Node interface indicators

Techniques for taking corrective action based on probabilities are provided. Request messages may include a size of a data packet and a stated issue interval. A probability of taking corrective action based on the size of the data packet, the stated issue interval, and a target issue interval may be retrieved. Corrective action may be taken with the retrieved probability.

Corrective actions based on probabilities

Techniques described herein provide for sending and receiving messages. The messages are associated with streams. Indicators associated with the streams determine if the messages are sent.

Indicators for streams associated with messages

A system comprises a processor, a reassembly buffer that receives mini-packets, and at least one data structure that comprises bits. The bits indicate the presence or absence of each of the mini-packets in the reassembly buffer and further indicate whether one of the mini-packets is a final mini-packet in a series of the mini-packets. The processor uses the bits to determine whether all mini-packets forming the series are present in the reassembly buffer. As a result of the determination, the processor causes the series to be read from the reassembly buffer.

Reassembly of mini-packets in a buffer

Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches).

Processing element having dual control stores to minimize branch latency

The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

Method for allowing distributed high performance coherent memory with full error containment

Systems, methods, and machine-readable media are disclosed for routing communications to a storage area network (SAN). In one embodiment, the machine-readable media includes first program code to determine a route path through a gateway to a SAN for each of a plurality of addresses of an interface of a server. The first program code determines the route path by applying an algorithm to one or more numerical values associated with the address. The machine-readable media includes second program code to configure the gateway with the route paths.

Routing communications to a storage area network

In a multitasking computer system, data is preloaded into cache memory upon the occurrence of a context switch. To this end, processing circuitry stops executing a computer program during a first context switch in response to a first context switch command. Later, the processing circuitry resumes executing the computer program during a second context switch in response to a second context switch command. The memory control circuitry, in response to the second context switch command, identifies an address of computer memory that is storing a data value previously used to execute an instruction of the computer program prior to the first context switch. The memory control circuitry then retrieves the data value from the computer memory and stores the retrieved data value in the cache memory. Accordingly, the retrieved data value is available to the processing circuitry for use in executing instructions of the computer program after the second context switch without the processing circuitry having to request retrieval of the foregoing data value.

System and method for preloading cache memory in response to an occurrence of a context switch

Method and apparatus for conditioning program control flow on the presence of requested data in a cache memory. In a data processing system that includes a cache memory and a system memory coupled to a processor, in various embodiments program control flow is conditionally changed based on whether the data referenced in an instruction are present in the cache memory. When an instruction that includes a data reference and an alternate control path is executed, the control flow of the program is changed in accordance with the alternate control path if the referenced data are not present in the cache memory. The alternate control path is either explicitly specified or implicit in the instruction.

Program control flow conditioned on presence of requested data in cache memory

Growing community of inventors

Roseville, CA, United States of America

Michael L Ziegler