Cisco Technology, Inc.

Michael L Wright

Kenneth Michael Key

Darren R Kerr

William E Jennings

John William Marshall

William Robert Lee

Vincent L Deters

Martin Hughes

Scott Nellenbach

Sriram Haridas

Hong-Man Wu

John David Billing

Gail Gyurek

Joydeep Chowdhury

William Fredenburg

Kenneth Harvey Potter, Jr

Kenneth H Potter

Jeffery B Scott

Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Network protocol header alignment

A method is provided in one example embodiment and includes receiving at a network element having a binding table a packet that is part of a flow, the binding table having an entry corresponding to the flow, the entry mapping the flow to a first one of a plurality of endpoints and recognizing that a state of the first one of the plurality of endpoints at the first network element is not active. The method further includes, determining that the state of the first one of the plurality of endpoints at a second network element mated with the first network element and having a binding table similar to the binding table of the first network element is active. The method still further includes, directing the flow to the first one of the plurality of endpoints via the second network element.

System and method for providing deterministic routing in a network environment

A method is provided in one example embodiment and includes receiving a packet that is part of a flow, and identifying parameters within the packet for mapping the packet to a selected endpoint amongst a plurality of endpoints. The method further includes generating a first binding table that reflects the packet being associated with the selected endpoint, and identifying that the selected endpoint has changed state. An update message is communicated to a peer network element, the update message directing the peer network element to rebuild a peer binding table to reflect the changed state. In more specific embodiments, the binding tables include matching entries for the selected endpoint and the flow. One of the parameters can be a Signaling System Number 7 (SS7) parameter within the packet.

A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Programmable arrayed processing engine architecture for a network switch

Method and apparatus for classifying a network protocol and aligning a network protocol header relative to cache line boundary

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient 'context' data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Architecture for a processor complex of an arrayed pipelined processing engine

Short messages are formatted as control messages in a communication network but do not control the communication network. Techniques for dynamically distributing short messages include remotely reprogramming a control node that processes control messages for the communications network to change processing of short messages without further involvement by a vendor of the control node. In some embodiments, this involves sending provider data that includes a special parameter set, a special value set, and a special action set. The special parameter set includes at least one parameter among multiple parameters in multiple network protocol headers for a data packet that includes a short message. The special value set includes at least one value for each parameter in the special parameter set. The special action set includes at least one action of multiple actions for forwarding a short message.

Method and system for customizing distributed short message routing

The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.

Multi-link protocol reassembly assist in a parallel 1-D systolic array system

Techniques for dynamically distributing short messages include storing action data and parameter data. Action data indicates actions for forwarding a short message and includes an action to bypass a short message service center (SMSC). Parameter data indicates parameters in network protocol headers for a short message. Provider input data is received that indicates a special value set and a special action set. The special value set includes a value for a corresponding special parameter set that includes a parameter from the parameter data. The special action set includes an action to be performed if an actual value set matches the special value set. When a particular short message is received, it is determined whether an actual value set based on the particular short message matches the special value set. If so, then the short message is processed according to the special action set.

A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Processor isolation technique for integrated multi-processor systems

The present invention comprises a scheduling assist function (scheduling assist) that enables a processor to schedule events and be notified when these events expire. In addition, the present invention includes features that enable a processor to associate these events with output channels and enable the processor to quickly locate output channels (links) that are available and ready to be serviced. The invention takes advantage of the fact that the scheduling assist can be dedicated exclusively to scanning tables in its own dedicated memories looking for events that have expired and/or output channels that are available and not involve the processor in the search for output channels that are available and ready to be serviced.

Scheduling assist for data networking packet dequeuing in a parallel 1-D systolic array system

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient &ldquo;context&rdquo; data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

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Raleigh, NC, United States of America

Michael L Wright