Cray Incorporated

Michael L Steinberger

David R Resnick

Van L Snyder

Gerald A Schwoerer

Roger A Bethard

Kelly J Marquardt

Alan M Grossmeier

Christopher Keith White

Michael Higgins

Raymond J Farbarik

R Paul Dixon

Ricky J Hakes

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the 'golden' MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Memory-daughter-card-testing method and apparatus

An apparatus comprising a transmission line, a receiver circuit, and a high pass filter circuit coupled between the transmission line and a receiver circuit input. The receiver circuit is configured to receive a data signal over the transmission line at a first data rate. The high pass filter circuit is connected between the transmission line and a receiver circuit input and has a corner frequency that is less than approximately the first data rate and is greater or equal to than approximately one-half the second data rate. The second data rate is an effective data rate caused by an expected data pattern on the transmission line. Other devices, systems, and methods are disclosed.

Lonely pulse compensation

Memory-daughter-card-testing apparatus and method

An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed.

Phase rotator for delay locked loop based SerDes

A memory controller and method that provide a read-refresh (also called 'distributed-refresh') mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Apparatus and method for memory with bit swapping on the fly and testing

Apparatus and method for testing memory cards

Growing community of inventors

Chippewa Falls, WI, United States of America

Michael L Steinberger