University of Rochester

Other

Compaq Computer Corporation, Inc.

Michael L Scott

Sandhya Dwarkadas

Grigorios Magklis

Rajeev Balasubramonian

David H Albonesi

Greg P Semeraro

Arrvindh Shriraman

Galen Clyde Hunt

Virendra J Marathe

Leonidas Kontothanassis

Michael F Spear

Nikos Hardavellas

Robert Stets

The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.

Mechanism to support flexible decoupled transactional memory

In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks&#x2014;conflict detection, validation, and data isolation&#x2014;for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.

System and method for hardware acceleration of a software transactional memory

A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.

Multiple clock domain microprocessor

A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Queue-based spin lock with timeout

The present invention discloses an apparatus and method for maintaining the coherence of data within a shared memory network including a plurality of nodes. The system utilizes processors monitoring the occurrence of particular processing events within a local memory storage area. Upon the detection of events indicating the change of status of a particular group of data, a comparison is made between a modified copy of the group of data and a clean copy of the group of data to detect any modifications made to the group of data. These modifications are entered into the clean copy of the group of data and processing continues.

Apparatus and method for maintaining data coherence within a cluster of symmetric multiprocessors

Growing community of inventors

Rochester, NY, United States of America

Michael L Scott