Apple Inc.

Michael L Regal

James D Kelly

Charles M Flaig

A mechanism is provided for reorderingReorderingbus transactionsto increaseincreasesbus utilizationin a computer system in whichwherea split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; inanother embodiment,the system is more loosely coupled withonly mastersbeingareordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would,result in deadlockif a predetermined further transaction were to begin,result in deadlock,this condition is detected. In the more tightly coupled system, the predetermined further transaction, if itisrefused ifrequested,is refused, therebyavoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case,reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the furthertransactionstransactionis killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis.In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

Bus transaction reordering in a computer system having unordered slaves

A method and system for selectively permitting address values to pass between two buses. Portions of the address values are used to select data in a mask register. The determination of whether to pass the address value is made on the basis of the mask register value ultimately selected.

Bus interface with address mask register for transferring selected data from one bus to another

A mechanism is provided for avoiding deadlock in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In accordance with another embodiment of the invention, the bus bridge detects when a state of the split-transaction bus would, if a protocol of said split-transaction bus were adhered to, result in deadlock. The bus bridge then drives one or more signals on the split-transaction bus in disregard of the protocol of the split-transaction bus, thereby avoiding deadlock. In accordance with still a further embodiment of the invention, transactions accepted within the bus bridge are monitored. When a combination of said transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock.

Deadlock avoidance in a split-bus computer system

A method of and apparatus for interfacing two systems which may not be operating in the same Endian mode. In one embodiment, the system generates both a transformed address information segment and an untransformed information segment and supplies one or the other to an address generator depending on whether Endian modes match.

Method and apparatus for interfacing two systems operating in

An interface between two buses in different clock domains. The interface includes a master buffer which is used for both master writes and slave reads. A control logic unit for each bus receives signals from a buffer manager which straddles the clock domains to gate latch pulses to the master buffer.

Master oriented bus bridge

A method for determining whether a bus interface should immediately acknowledge a read request. In one embodiment, devices connected to a plurality of buses are assigned addresses from a first set of addresses or a second set of addresses depending upon whether the device will accept a read request within a predetermined period of time. The bus interface immediately acknowledges a read request directed toward a device with an address in the first set of addresses and delays the acknowledgement for a read request directed toward a device with an address in the second set of addresses.

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Campbell, CA, United States of America

Michael L Regal