Madrone Solutions, Inc.

Dell USA L P

Other

Intel Corporation

Motorola Corporation

Advanced Micro Devices Corporation

Dell Corporate Services Corporation

Michael L Longwell

William Daune Atwell

Jeffrey Van Myers

Terry J Parks

Keith D Matteson

Darius D Gaskins

James Robert Feddeler

Zahid Ahsanullah

Paul F Groepler

Thomas H Holman, Jr

Joseph Patrick Geisler

William D Atwell, Jr

Clyde H Browning, Iii

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

Method and apparatus for error detection and correction

A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.

Controlling signal states and leakage current during a sleep mode

An apparatus for operating a dynamic memory ( ) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

Apparatus for operating an integrated circuit having a sleep mode

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

Method for apparatus for tracking errors in a memory system

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provide the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( ). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( &Prime;).

Memory tile for use in a tiled memory

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provided the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( 41 ).

Tiled memory and memory tile for use therein

A method for operating a dynamic memory ( ) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

Method for operating an integrated circuit having a sleep mode

In one embodiment, a plurality of atomic charge pumps (,) are connected together in series to form a distributed charge source (,). The atomic charge pumps (,) are operated sequentially over time to reduce supply signal noise. In addition, the distibuted charge source (,) is compatible with low power applications because each atomic charge pump (,) can be independently powered down if it is not required.

Distributed charge source

A plurality of memory tiles (,) are arranged to form a tiled memory array (,) in an integrated circuit device (,). In accordance with the present invention, each of the memory tiles (,) in the tiled memory array (,) has charge source circuitry (,) to provide the sufficient reference voltages for proper operation of the memory tile (,). In addition, each memory tile (,) may include local error detection and correction circuitry (,). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (,&Prime;).

Method for designing a tiled memory

A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c').

Method for designing a memory tile for use in a tiled memory

A digital computer which includes a memory refresh system for controlling the generation and sequencing of refresh signals to a memory subsystem comprised of at least one memory unit having a plurality of slots each capable of receiving a dynamic random access memory bank therein. The memory refresh system includes means for generating refresh signals and at least one independent refresh sequence controller for efficiently controlling the sequence in which the memory banks associated with a particular refresh sequence controller receive refresh signals. Each refresh sequence controller controls a combination of multi-stage shift registers for issuing refresh signals to memory banks installed on the corresponding memory unit and multi-stage shift registers for providing wait cycles during which refresh signals are being generated by other independent refresh sequence controllers. The order of refresh signals generated by each refresh sequence controller varies depending on the configuration of the memory subsystem.

Digital computer having a system for sequentially refreshing an

An apparatus is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge driver which precharges alternating pairs of conductors to opposite rail voltages. By precharging pairs of conductors to alternating rails, the present apparatus can minimize the speed degradation problems associated with a transitioning target conductor within the bus. Precharging alternating pairs of conductors also minimizes crosstalk noise from transitioning neighbor conductors to a non-transitioning target conductor. The improved dynamic bus thereby demonstrates improvements in speed degradation and crosstalk noise as seen by a transitioning target conductor or non-transitioning target conductor, respectively.

Apparatus and method for precharging bus conductors to minimize both

A digital computer system has an error correction code (ECC) syndrome encoder for generating initial ECC syndromes from digital words input to the system which are received together with their corresponding ECC syndromes, in the system receiving circuitry. The system has an ECC syndrome re-encoder for generating second ECC syndromes from the digital words as they are removed from the receiving circuitry. A comparison circuit then compares the originally encoded syndrome with the re-encoded syndrome as it is being generated, to detect whether there is a difference and therefore an error in the digital word or an error in the syndrome. The comparison circuit is integrated into and is a part of the ECC re-encoder.

Growing community of inventors

Austin, TX, United States of America

Michael L Longwell