Unisys Corporation

Other

Michael L Haupt

Mitchell A Bauman

Roger Lee Gilbertson

Lewis A Boone

Eugene A Rodi

Penny L Svenkeson

Kenichi Tsuchiya

James L Depenning

Donald R Kalvestrand

Thomas John Adelmeyer

Daniel S Tokoly

Frederick George Fellenser

Maria A Liedman

Doug A Fuller

Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions

A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as &ldquo;deferred&rdquo; requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure. According to one aspect of the invention, all deferred requests requesting access to the same main memory address are stored as a linked list of requests in the temporary storage structure. Requests are processed by main memory in a first-in, first-out manner such that the oldest requests are completed before more recently-received requests. According to another aspect of the invention, the request management system further handles I/O overwrite operations wherein a peripheral device is allowed to overwrite requested addresses within the main memory even though the most recent copy of the data associated with some of the overwritten memory addresses is stored within ones of the cache memories. To process the I/O overwrite operations in a manner that preserves data coherency, the I/O overwrite requests are deferred in a manner that is similar to cache-initiated requests. Specifically, I/O overwrite requests made to an address associated with any previously-deferred I/O overwrite or cache-initiated requests are deferred until all such previously-deferred requests are processed by main memory.

System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme

A method and apparatus for scheduling the execution of selected requests received in a first-in-time sequence, such that two or more request types are executed in a particular sequence for increased performance. Briefly, the present invention identifies two or more requests that have two or more predetermined request types, and schedules the identified requests in an order that corresponds to the particular sequence.

Method and apparatus for scheduling requests within a data processing system

A data processing system and method for substituting selected requests with substitute requests that perform the same or similar end function but achieve increased system performance are disclosed. Those requests that have a selected request characteristic are identified and converted or replaced with a predetermined substitute request. The substitute requests perform at least part of the function of the identified requests. The data processing system may include two or more processors, and the selected request characteristic may be that a write data packet of an identified write request was not changed by a first processor. A substitute request may update directory information associated with the identified write request but may not write to associated data packet to memory. The directory information can indicate whether identified memory locations are currently owned by a processor. The substitute request may also send the associated write data packet from the first processor to a second processor via a processor-to-processor interface. It may be determined whether a processor block has changed selected data by examining a function code of a write type request.

Data processing system and method for substituting one type of request for another for increased performance when processing back-to-back requests of certain types

A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device. A purge command is issued to the first device to invalidate the copy of the requested data segment in the first local memory. Upon issuance of the purge command to the first device, a purge acknowledge response is delivered to the second device, where the purge acknowledge response provides an indication that the copy of the requested data in the first local memory has been invalidated. The second device is prohibited from releasing any modified data until the purge acknowledge response is received.

System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency

A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first device to a second local memory in a second device in a transaction processing system that includes a main memory to provide supervisory storage capability for the transaction processing system, and a directory storage for maintaining ownership status of each data segment of the main memory. A data transfer of a requested data segment is requested by the second device to obtain the requested data segment stored in the first local memory of the first device. The requested data segment is removed from the first local memory in response to the data transfer request, and is directly transferred to the second local memory of the second device. The requested data segment is also transferred to the main memory, and to the directory storage where the ownership status can be revised to reflect a change of ownership from the first device to the second device. The direct transfer of the requested data segment between the first and second devices occurs independently of the transfer of the requested data segment from the first device to the main memory and directory storage.

System and method for bypassing supervisory memory intervention for data

A method and apparatus for providing a multi-source reset for independent partitions within a multiprocessor computer system. In a system having at least two partitions wherein the at least two partitions share interconnect hardware, a reset may be provided to a first one of the at least two partitions while allowing the remaining of the at least two partitions to continue to operate. The interconnect hardware may provide means for reseting a first portion of the interconnect hardware associated with the first partition while allowing the remaining portions of the interconnect hardware to continue to operate undisturbed. The reset function may be triggered by hardware or software in either partition or by a system control facility.

Reset for independent partitions within a computer system

A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level. Hysteresis is provided to allow time for the power sourcing circuitry to recharge before discontinuing the delays.

Dynamic power regulator for controlling memory power consumption

A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared intermediate level cache modules. The technique provides the band pass and attendant performance advantages of an essentially point-to-point architecture without all of the added hardware of a centralized master system storage controller. Further, unlike a strictly point-to-point architecture, the present invention is readily expandable to service a large number of multiprocessors without burdening each of the multiprocessors with the corresponding increase in interface and connection costs of a strictly point-to-point architecture. This simplifies the design of the multiprocessor elements and also allows a system to be expanded to include more or less multiprocessors by simply including a modified XBAR interface. In a strictly point-to-point architecture, the multiprocessors may have to be modified to expanding a system because the interfacing circuitry associated therewith is contained therein. The present invention further has a means for increasing the performance of the XBAR interface by providing an anticipatory acknowledge signal back to a requesting multiprocessor.

Cache coherency scheme for XBAR storage structure with delayed

A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition. The block buffer has a no save designator for block transfers and other accesses for which near term subsequent access to buffered data is unlikely. Data designated no save is not transferred from the block buffer to the cache memory.

Growing community of inventors

Roseville, MN, United States of America

Michael L Haupt