Cypress Semiconductor Corporation

Silicon Laboratories Inc.

Crystal Semiconductor Corporation

Michael L Duffy

Navdeep S Sooch

Mohammad J Navabi

Michael James Mills

Douglas S Piasecki

Nathan Y Moyal

Bertrand Jeffery Williams

Paul H Scott

Marty Lynn Pflum

Ion Constantin Tesu

Jing Li

Zhiwei Dong

John Nathaniel Wilson

Tufan C Karalar

András Vince Horvath

Michael Keith Odland

Ross Sabolcik

Phillip J Kruczkowski

Jaideep Prakash

Long Nguyen

Paulo Santos

James H Jones

Rudye McGlothlin

An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

Adjustable soft shutdown and current booster for gate driver

An apparatus for controlling a high-power drive device external to a package of a motor drive circuit includes a motor drive circuit. The motor drive circuit includes a driver to control the high-power drive device based on a first reference voltage, a second reference voltage, and a control signal based on a received control signal. A fault circuit generates a failure indicator based on a voltage across terminals of the high-power drive device. A fault condition is based on the failure indicator. A first terminal coupled to the driver charges a node of the high-power drive device over a first length of time in response to an absence of the fault condition and a first level of the control signal. A second terminal coupled to the driver discharges the node over a second length of time different from the first length of time.

Soft shutdown for isolated drivers

One aspect of the present invention is directed to a circuit that includes an amplifier circuit disposed between an isolation link and a Schmitt trigger circuit to amplify a differential signal communicated over the isolation link and supply the amplified signal to the Schmitt trigger circuit. In turn, the Schmitt trigger circuit is coupled to the amplifier circuit to receive the differential signal and to supply a differential output signal corresponding to the differential signal communicated over the isolation link.

Capacitive isolation receiver circuitry

A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.

Low power metering using pulse counting

A scheme (e.g., one or more methods, circuits and/or architectures) for detecting the difference in frequencies between two periodic (e.g., clock) signals and/or for reliably assuring the frequency of an oscillating circuit (e.g., a voltage controlled oscillator [VCO], a phase locked loop [PLL] containing a VCO, etc.). The present invention is particularly useful for clock recovery in data communications devices and more particularly in asynchronous transfer mode (ATM) devices, such as SONET/SDH transmitters, receivers and/or transceivers.

Frequency difference detector with hysteresis

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.

Data transmitter with sequential serialization

A parallel sampling phase detector with linear output response. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five &ldquo;window&rdquo; intervals. The &ldquo;window&rdquo; intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective &ldquo;window&rdquo; signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Phase locked loop (PLL) with linear parallel sampling phase detector

An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

Low latency, low power deserializer

An apparatus comprising a first circuit configured to present one or more control indication signals and (ii) a control clock signal in response to (i) one or more select signals, (ii) one or more clock signals and (iii) one or more divider control signals. The first circuit may be configured to select an active channel from a plurality of channels in response to the one or more select signals.

Frequency difference detector with programmable channel selection

A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

Differential charge pump

An apparatus comprising a first circuit and a deserializer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may be configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals.

An apparatus comprising a phase-locked loop, a select circuit and a control circuit. The phase-locked loop may be configured to generate a feedback signal (along with a buffered output signal) in response to a reference clock and a control signal. A select circuit may be configured to present a reference clock signal in response to a plurality of input clock signals and a select signal. The slew control circuit may be configured to generate the control signal in response to the select signal, and the feedback signal. The control circuit may be used to reduce noise presented to the phase-locked loop and may allow for a rapid initial frequency acquisition of the PLL to the reference frequency.

Circuit, architecture and method(s) of controlling a periodic signal

A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five 'window' intervals. The 'window' intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective 'window' signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector is disclosed for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five 'window' intervals. The 'window' intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective 'window' signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Phase detector with linear output response

A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a '0' value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56). The contents of the latch (56) are input to a summing junction (54) which, in normal operation, are summed with the output of the interpolation circuit (40) for input to the delta-sigma converter (44). By disposing the summing junction (54) between the interpolation circuit (40) and the delta-sigma modulator (44), the bit load on the input of the interpolation (40) can be reduced. By utilizing the interpolation circuit (40) in the calibration procedure, the gain thereof can be compensated for in the value stored in the register/latch (56).

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Austin, TX, United States of America

Michael L Duffy