Infineon Technologies Ag

Qimonda Ag

Altis Semiconductor, Snc

Siemens Aktiengesellschaft

Michael Kund

Thomas Happ

Ralf Symanczyk

Thomas Roehr

Franz Kreupl

Ulrich Karl Klostermann

Christian Pacha

Klaus-Dieter Ufert

Cay-Uwe Pinnow

Corvin Liaw

Joerg Berthold

Tim Schoenauer

Georg Müller

Alexander Duch

Tim Schönauer

Rolf Weis

Dieter Draxelmayr

Gerhard Mueller

Dominique Savignac

Heinz Hoenigschmid

Christoph Ludwig

Winfried Kamp

Ulrike Gruening-von Schwerin

Bernhard Ruf

Petra Majewski

Wolfgang Nikutta

Dieter Andres

Thomas Niedermeier

Michael Hübner

Stephan Appen

Reinhard Salchner

Jan Ten Br&ouml;ke

Rainer Bruchhaus

Christian Ruester

GillYong Lee

Martin Keim

Abel Rios-Baez

A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Resistive memory and method

An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

According to one embodiment of the present invention, a temperature sensor is provided, including a first electrode, a second electrode, a nanoporous material disposed between the first electrode and the second electrode, and a diffusion material which is located outside the nanoporous material that is capable of diffusion into the nanoporous material. The amount of diffusion material diffusing into the nanoporous material is dependent on the temperature to which the temperature sensor is exposed. The resistance of the nanoporous material is dependent on the amount of diffusion material diffusing into the nanoporous material.

Temperature sensor, integrated circuit, memory module, and method of collecting temperature treatment data

An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.

Carbon filament memory and fabrication method

An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.

Electric device protection circuit and method for protecting an electric device

A tunable resistor includes a resistor input terminal, a resistor output terminal, and at least one current path connected between the resistor input terminal and the resistor output terminal. The at least one current path runs through at least one memory cell of an arrangement of programmable microelectronic memory cells. A resistance adjuster adjusts the current path resistances of the current paths by programming the memory states of corresponding memory cells or which activates/deactivates current paths such that the overall resistance between the resistor input terminal and the resistor output terminal is set to a predetermined resistance target value.

Tunable resistor and method for operating a tunable resistor

Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Resistive memory arrangement

A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Integrated circuit including sub-lithographic structures

The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

Write/delete process for resistive switching memory components

Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.

Nonvolatile memory cell

The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.

Memory device electrode with a surface structure

Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).

Intergrated circuit for programming resistive memory cells

A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.

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Tuntenhausen, Germany

Michael Kund