Zipalog Inc.

Texas Instruments Corporation

Lennox Industries Inc.

Hampton Products International Corporation

Michael Krasnicki

Felicia James

Xiyuan Wu

Yue Deng

Stephen J Vendt

Jon Fong Quan

Steve Lazar

Surendran Ramasamy

Melissa Amoros

Howard Shen

Arun Kunasekaran

Bruce K Lee

Minas Hambardzumyan

Ryan W Eatmon

Jose Luis Vega

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Computer implemented system and method of translation of verification commands of an electronic design

A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.

Computer implemented system and method of identification of useful untested states of an electronic design

HVAC controller housing

Methods and systems are provided for pairing electronic devices. One method includes generating a code sequence for pairing an electronic device with an application executed by a processor of a controller, the controller being remote to the electronic device, and the electronic device and the controller interfacing with a server via a network connection. The code sequence includes a configuration mode portion indicating a role for a user of the controller, an invitation sequence having invitation code for the user and a random code portion. The method further includes receiving the code sequence by the electronic device; validating the code sequence by the electronic device using a key data structure; and pairing the electronic device to the controller for enabling the application to monitor and command the electronic device.

Secured tethering process between devices

A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation. Useful untested states are identified based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.

A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of the first parameter of the first input data of the at least one first system and first subsystem in said first design file to the analysis of the first input parameter of the second input data of the least one second system and second subsystem in the second design file and repeating the comparison for a series of input parameters to build a history of verification coverage of input parameters of the at least one second system and second subsystem of the second design file relative to the at least one first system and first subsystem of the first design file.

System and method for passive verification

A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog. First and second output subsystem data is collected from at least one output of the first and second subsystem design representation of the at least two design representations caused by the analog stimulus to the at least one input of the first and second subsystem design representation. At least one parameter of said first and second input subsystem data is analyzed with respect to said first and second output subsystem data. The at least one parameter of the first subsystem design representation is compared with the at least one parameter of second subsystem design representation. The electronic design file of the electronic design is verified responsive to the determined analysis between the at least one input of the subsystem and the at least one output of the subsystem for each of the first and the second subsystem design representations.

Circuit analysis software packages are a significant tool used today in the design of integrated circuits (ICs). Many of the conventional and commercially available simulation or analysis packages, however, are limited to performing static design 'checks' using topology based search algorithms to find potential problems in a subject design. Here, a system is provided that allows a user to define parameters that comport with the subject design to generate a set of specific topologies from a set of generic topologies. These generated topologies can then be used to perform a more thorough analysis of the subject design.

Method and system for defining generic topologies for use in topology matching engines

A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.

Passive verification, comprising, receiving a representation of an electronic design comprised at least in part of at least system having at least one subsystem which is analog, collecting at least one input subsystem level data, having at least one input subsystem signal marker, collecting at least one output subsystem level data, having at least one output subsystem signal marker and analyzing at least one measure of at least one of the at least one input subsystem signal marker and at least one output subsystem signal marker.

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Richardson, TX, United States of America

Michael Krasnicki