Hewlett-Packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Michael Knowles

Jeffrey A Sprouse

Tom A Heynemann

David J Garcia

Peter H Duong

In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.

Delegated write for race avoidance in a processor

A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect

A peripheral control interface provides access to a system area network for a plurality of peripheral devices connected to the PCI through an I/O bus. A plurality of virtual data channels is defined in local memory to which outstanding requests from peripherals are assigned. Physical channel engines implement the order requests through the assigned virtual data channel with accessed data stored in local memory. A subsequent request by a peripheral can then be immediately fulfilled from data stored in memory. Data channel context stored in memory includes the number of outstanding requests by a user to whom the channel is dedicated, and a physical channel engine can pre-fetch data in response to a plurality of outstanding requests from a peripheral thereby eliminating latency in fulfilling requests.

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Santa Clara, CA, United States of America

Michael Knowles