International Business Machines Corporation

United States of America As Represented by the Secretary of the Air Force

Michael Kevin Ciraula

George McNeil Lattimore

Christopher McCall Durham

Donald George Mikan, Jr

Gus Wai-Yan Yeung

Derwin L Jallice

Sang Hoo Dhong

Robert Paul Masleid

Manoj N Kumar

Dieter F Wendel

Terry Lee Leasure

David James Martens

Hung Qui Le

Joel Abraham Silberman

Peter Juergen Klim

John Stephen Muhich

Hoichi Cheong

Terry I Chappell

John Beck

Larry Edward Thatcher

Rudolf Adriaan Haring

Mark S Milshtein

Andrew Augustus Bjorksten

Visweswara Rao Kodali

Friedrich C Wernicke

Talal K Jaber

Gus Wai-Yen Yeung

Friedrich-Christian Wernicke

Joseph M Poplawski, Jr

Edward Seewann

Craig L Stephen

Max Eduardo De Ycaza

Pho Hoang Nguyen

Reginald E Harrison

Derwin J Jallice

Christopher Mc Durham

Dave C Lawson

The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.

Elimination of SOI parasitic bipolar effect

A dynamic switching circuit for use in a domino circuit array is disclosed. The dynamic switching circuit includes a charge-saving transistor for preventing charge stored on the dynamic circuit's output node from discharging to ground. The charge stored on the output node is then fed back to a precharge control transistor to charge the dynamic node during the subsequent precharge/evaluate cycle.

Power-saving dynamic circuit

An anti-charge share device and method for operation ensure that charge share protection is provided for nodes in a logic circuit during an evaluate stage with low costs in terms of power and circuit performance. The anti-charge sharing device includes a transistor coupled between pre-charge node and a second node being evaluated. By coupling the charge share device between the pre-charge node and the node to be evaluated, operation of the charge share device is dependent upon a node which no longer requires a charge-sharing protection.

Circuit having anti-charge share characteristics and method therefore

A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.

Conditional restore for RAM based on feedback from a RAM cell to

A system and method for initializing a threshold voltage level of a dynamic circuit prior to a transition of said dynamic circuit from a passive mode to an active mode. A dynamic logic circuit has a runtime operation that alternates between an active and a passive mode and includes at least one transistor having a floating body and a threshold voltage level. A switching device within the dynamic logic circuit forms a means from which the floating body draws an electric charge during the passive mode, thereby altering the threshold voltage level. The switching device receives a clock input signal during the dynamic circuit's active mode. Input selection means selectively replace the clock input signal with a pre-clock input signal into the switching device for a pre-determined period of time prior to a transition by the dynamic logic circuit from the passive mode to the active mode, such that the floating body may adequately discharge, thereby initializing the threshold voltage level prior to commencement of the active mode.

Initialization of floating body dynamic circuitry

An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter includes a data selection mechanism, the data selection mechanism receiving a data cache line of a predetermined organization, and the data selection mechanism further supporting adjacent word swapping in the cache line. The load data formatter further includes at least two word selectors coupled to an output of the data selection mechanism, the at least two word selectors forming a doubleword on a chosen word boundary of the cache line. In a further aspect, the predetermined organization of the cache line is provided by grouping each corresponding bit of each byte in a cache line of data together, and expanding the grouping with an organization formed by one bit from a same byte within each word. The at least two word selectors may comprise even and odd multiplexers, and the load data formatter may also include splice registers, coupled to an output of one of the at least two selectors, which provide formatting of unaligned load access across a cache line boundary.

Method and system for load data formatting and improved method for cache

A novel SRAM construction allows for reduced power consumption by conditionally restoring only these memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.

Conditional restore for SRAM

A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.

Memory array and method for writing data to memory

A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock). In an embodiment wherein the execution unit has two operand multiplexers which receive the data input, the evaluation circuit includes two select line respectively connected to the multiplexers, and to inputs of the AND gate. In an alternative embodiment wherein the execution unit has data output in the form of a TRUE line and a COMPLEMENTARY line, the evaluation circuit includes a NOR gate means having a first input connected to said TRUE line, a second input connected to said COMPLEMENTARY line, and an output connected to said first input of the AND gate.

Conditional restore for execution unit

A combined adder/decoder calculates a field within an effective address necessary to access a translation array. Rather than adding the full lengths of the previous fetch address and offset, only the bits corresponding to the field are added. A carry-in value from less significant bits is concurrently generated. Based on the sum result, two wordlines are chosen: the wordline corresponding to the sum result calculated and the next higher wordline. The carry-in value is used to select the appropriate wordline from the chosen pair. Because fewer bits are added and the carry-in need not be accounted for in the adder, the generation and decoding processes are faster and allow address translation to be started earlier in the processor cycle.

Translation shadow array adder-decoder circuit for selecting consecutive

A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.

High performance registers for pulsed logic

A method and implementing structure for a domino block circuit 200 includes a minimal component latching circuit 203 which is merged with an exemplary MUX functional block 201, to provide both inverting and latching functions with minimal propagation delay in the domino data path. Implementations with scanning circuitry and including a holding feature are also illustrated.

Latch structure for ripple domino logic

The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.

System and method for testing self-timed memory arrays

A method and implementing structures for a domino block circuit configuration includes a plurality of domino logic blocks including inverter circuits to provide inverted signals which are needed for a comprehensive logic analysis and processing. A plurality of clocking signals are applied at various clocking inputs throughout the circuit. The clocking signals are timed relative to each other in a timing sequence to assure that the logic circuit evaluations occur only after relevant data and switching signals have stabilized.

Creating inversions in ripple domino logic

The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.

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Round Rock, TX, United States of America

Michael Kevin Ciraula