Qualcomm Incorporated

Michael Kevin Batenburg

Ron Keidar

Vincent Pierre Le Roy

Praveen Kumar Origanti

Osman Koyuncu

Esin Terzioglu

Gregory Ameriada Uvieghara

Steven Mark Millendorf

Yucong Tao

Sarath Chandra Kasarla

Steven M Millendorf

In certain aspects of the disclosure, a system includes an isolation device coupled between a first circuit in a first power domain and a second circuit in a second power domain. The system also includes a second power source coupled to a power distribution network, wherein the power distribution network is configured to distribute power from a first power source to the second power domain. The system further includes a failure detector having an input coupled to a node on the power distribution network located upstream of the second power source, and an output coupled to the isolation device, wherein the failure detector is configured to sense a voltage at the node, to detect a power loss of the first power source based on the sensed voltage, and to enable the isolation device in response to detection of the power loss.

Methods for detecting an imminent power failure in time to protect local design state

In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.

In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.

Method, apparatus, and system for semaphore-based protection of power-domain-crossing signals

System and method for providing adaptive access to a hardware block on a computer system. In one embodiment, a method includes receiving a first access request and a second access request with an access controller, wherein the second access request is received sequentially after the first access request, and the first access request includes a first master identification and the second access request includes a second master identification, determining if the second master identification is equal to the first master identification, providing access to the second access request if the second master identification is equal to the first master identification, wherein the first master identification is associated with one or more hardware block interface values, invalidating the one or more hardware block interface values associated with the first master identification if the second master identification is not equal to the first master identification, and associating the one or more hardware block interface values with the second master identification and a corresponding privilege.

Adaptive access control for hardware blocks

Disclosed is an apparatus and method to set the speed of a clock. A computing device may include a processor and a scheduler of the processor, the scheduler may be configured to: receive a plurality of votes for requested bandwidths from a plurality of different execution environments; sum the requested bandwidths; and set the clock speed based upon the sum of the requested bandwidths.

Apparatus and method to set the speed of a clock

Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Protection for system configuration information

A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.

Growing community of inventors

San Diego, CA, United States of America

Michael Kevin Batenburg