Hewlett-Packard Development Company, L.p.

Michael Kennard Tayler

Eric M Rentschler

Larry Jay Thayer

George Thomas Letey

Jeff G Hargis

Darel N Emmot

Eric R Delano

Erin Antony Handgen

Don D Josephson

Quanhong Zhu

Eri M Rentschler

Jonathan Q Smela

An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of the data groupings in the lower 72 bits of each memory expander. A second memory module receives all of the data groupings in the upper 72 bits of each memory expander. A failure in any one or more bytes in an ECC word indicate failures in the computer memory system.

Memory subsystems with fault isolation

Systems and methods for implementing chip correct and fault isolation in computer memory systems are disclosed. An exemplary method may include interleaving check bits with a data word to form at least one interleaved data word. The method may also include writing the at least one interleaved data word to memory in critical word order zero. The method may also include performing a check and correct operation on the at least one interleaved data word before returning the data word to a requesting device.

Chip correct and fault isolation in computer memory systems

The present invention is broadly directed to a integrated circuit component with a scalable architecture. In one embodiment, an integrated circuit component is provided comprising logic capable of being configured to interface with a first portion of a system bus, and logic capable of being configured to interface with a companion integrated circuit and to receive information that is communicated from the companion integrated circuit, which information was communicated to the companion integrated circuit via a second portion of the system bus.

Integrated circuit with a scalable high-bandwidth architecture

An integrated circuit component is provided comprising logic capable of being configured to interface with a first companion integrated circuit and to receive information that is communicated from the first companion integrated circuit, which information was communicated to the first companion integrated circuit via a first portion of a system bus. The integrated circuit component further comprises logic capable of being configured to interface with a second companion integrated circuit and to receive information that is communicated from the second companion integrated circuit, which information was communicated to the second companion integrated circuit via a second portion of the system bus

A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system also includes a plurality of trigger generators corresponding to the plurality of kinds of timeout events. Each of the plurality of trigger generators is associated with a corresponding timeout threshold value representing the minimum amount of time that must elapse for the trigger generator to generate a timeout event trigger. For each of the plurality of timeout triggers, a corresponding selection signal selects one of the plurality of periodic overflow signals. The timeout threshold corresponding to each timeout trigger is equal to the period of the corresponding selected overflow signal multiplied by the value of the corresponding control signal.

Timeout event trigger generation

A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A first error correction engine is provided for correcting device-level errors associated with a specific memory device and a second error correction engine for correcting errors at a memory module level, wherein the first and second error correction engines are operable in association with a memory controller operably coupled to the plurality of memory modules.

Hierarchical memory correction system and method

A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.

System and method for multi-modal memory controller system operation

Memory interface methods and apparatus for processing source synchronous data from a memory device (DRAM). The methods and apparatus synchronously transfer data from the memory device to a memory controller even though the time variability of read return strobe signals is greater than one clock cycle.

Memory interface methods and apparatus

The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.

Memory system and controller for same

Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.

RAID memory system

Embodiments of an edge detector and related methods are disclosed. One method embodiment for detecting the rising and/or falling edge of an input clock signal of unknown phase and frequency includes providing a reference clock signal of a known phase and frequency to an edge detection circuit; dividing and phase shifting the reference clock signal to provide a plurality of meta flip-flop clock signals; providing the plurality of meta flip-flop clock signals and an input clock signal to a plurality of flip-flop pairs that provide meta-stability resolution; selecting the earliest output signal of the plurality of flip-flop pairs to register a transition on the input clock signal; providing a signal corresponding to the transition to an edge detection circuit; and providing an edge detect indication at the edge detection circuit during one of the corresponding high and low phase of the input clock signal.

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Loveland, CO, United States of America

Michael Kennard Tayler