Linear Technology Corporation

Michael Keith Mayes

Todd S Kaplan

David Edward Bliss

Todd Stuart Kaplan

A method and a circuit take a measurement of a sensor having first, second and third lead wires by: (a) providing first, second and third terminals for voltage measurements; (b) connecting a current sensing device (e.g., a reference resistor) to provide a signal at the third terminal that is indicative of the current in the third lead wire of the sensor; (c) connecting a first protective device between the first lead wire of the sensor and the first terminal; (d) connecting a second protective device between the second lead wire of the sensor and the second terminal; (e) connecting a first current source to the first lead wire of the sensor; (f) connecting a second current source to the second lead wire of the sensor; and (g) measuring a first voltage across the first and second terminals and a second voltage across the third terminal and the voltage reference.

Circuit and arrangement for 3-wire measurements with input protection

An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.

Synchronized charge pump-driven input buffer and method

Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

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Michael Keith Mayes