International Business Machines Corporation

Michael Kazda

Lakshmi Narasimha Reddy

Paul Gerard Villarrubia

Harald Folberth

Arjen Alexander Mets

Frank Musante

Cindy ShuiKing Washburn

Nancy Y Zhou

Zhuo Li

Gi-Joon Nam

Diwesh Pandey

Gustavo Enrique Tellez

Michael H Wood

Alexander Joel Suess

Adam P Matheny

Ying Zhou

Sven Peyer

Louise Helen Trevillyan

Jesse Peter Surprise

Sean Michael Carey

Pooja M Kotecha

Gerald Strevig, Iii

Shawn Kollesar

Stephan Held

Pietro Saccardi

Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.

Netlist design for post silicon local clock controller timing improvement

To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Automated design closure with abutted hierarchy

Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.

Local clock buffer controller placement and connectivity

Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.

Placement of vectorized latches in hierarchical integrated circuit development

A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.

Dynamic microprocessor gate design tool for area/timing margin control

A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

Engineering change order aware global routing

Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining 'non-critical' circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical circuit components in a new partial placement image of said map; and reinserting the 'non -critical' circuit components back into said placement image. The optimization is performed by circuit transformation operating in congested regions of the placement image enabling cell insertion and modifications that increase cell size.

Method of improving timing critical cells for physical design in the presence of local placement congestion

A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets that satisfy at least one of the plurality of re-routing criteria. For each of the nets that satisfy at least one of the plurality of re-routing criteria: several operations are performed. The net is globally re-routed to determine a new global route for the net. Those of the nets that are within a given distance of the new global route are identified. The net is detail re-routed in accordance with the new global route without regard to those of the nets within the given distance of the new global route. Those of the nets within the given distance of the new global route are re-routed after completion of the detailed re-routing of the net.

Timing refinement re-routing

A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

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Poughkeepsie, NY, United States of America

Michael Kazda