Intel Corporation

Michael Kagan

Simcha Gochman

Itamar S Kazachinsky

Tal Gat

Shai Rotem

David Perlmutter

Benny Lavi

A multiprocessor computer system which maintains cache coherency includes first and second microprocessors each having an associated cache memory storing lines of data. Each line of data has associated protocol bits that indicate a protocol state consistent with write-through, write-back, or write-once cache coherency policies that are selected via a protocol selection terminal for different system configurations. In one configuration, the output and external address terminals of the first microprocessor are coupled to the external and output address terminals, respectively, of the second microprocessor. This configuration enables each microprocessor to snoop memory cycles to main memory initiated by the other microprocessor so that it can be readily determined if a particular cache has the latest version of data.

Cache coherency mechanism for multiprocessor computer systems

A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating a trap upon modification of the pipeline. Improved trap handling capabilities and improved overall system performance is provided by reducing unnecessary saving and restoring of the pipeline during certain trap handling procedures, such as those that do not modify the state of the pipeline.

Method and apparatus for controlling the saving of pipelines in

An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

Write ordering for microprocessor depending on cache hit and write

An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

Line buffer for cache memory

An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

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Haifa, Israel

Michael Kagan