Sun Microsystems, Inc.

Oracle America, Inc.

Cisco Technology, Inc.

Cabletron Systems, Inc.

Open Computing Trust I

Michael K Wong

Yatin Gajjar

Shimon Muller

Ariel Hendel

Rahoul Puri

Leslie D Kohn

May Lin

Kunle A Olukotun

David R Cheriton

Gregory Frederick Grohoski

Flavio Giovanni Bonomi

Aly E Orady

Paul Joseph Jordan

Andreas V Bechtolsheim

Rabin Sugumar

Anup K Sharma

Mohammad Kamel Issa

Ravinder Kumar

Jochen Behrens

Stephen Phillips

Hugh Kurth

Rahoul Pun

KunIe A Olukotun

Raju Penumatcha

Suraj Sudhir

A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

Simple, reliable, connectionless communication mechanism

A method for sharing a network interface among multiple hosts and includes providing a network interface, associating a first set of the plurality of memory access channels with a first host, and associating a second set of the plurality of memory access channels with a second host is disclosed. The network interface including a plurality of memory access channels.

Method for sharing interfaces among multiple domain environments with enhanced hooks for exclusiveness

A method and apparatus for efficient interrupt event notification for a scalable input/output device in a network system. A network interface unit is operably connected to a plurality of processing entities and associated memory units. At least one status register in the network interface unit contains information relating to a process to be performed by at least one processing entity communicated to the processing entity by an interrupt event notification. Shared memory space comprises a mailbox storage register operable to store an image of the interrupt information stored in the status register of the network interface unit. A processing entity can directly access the process information stored in the mailbox status register thereby reducing system latency associated with reading information in the status register. Updated process status information in the network interface status register may be read by the processing entity on an interleaved basis while executing a process.

Method and apparatus for efficient interrupt event notification for a scalable input/output device

A method of resolving mutex contention within a network interface unit which includes providing a plurality of memory access channels, and moving a thread via at least one of the plurality of memory access channels, the plurality of memory access channels allowing moving of the thread while avoiding mutex contention when moving the thread via the at least one of the plurality of memory access channels is disclosed.

Method for resolving mutex contention in a network system

A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Hiding system latencies in a throughput networking systems

A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.

Method and apparatus for separating and isolating control of processing entities in a network interface

Hiding system latencies in a throughput networking system

A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core. The asymmetrical data processing partitions are scalable by adding additional processing entities.

Method and apparatus for arbitrarily mapping functions to preassigned processing entities in a network system

A method of performing a lookup within a network interface unit which includes providing a plurality of memory access channels, performing a multilayer lookup operation on a packet, and refining a selection of one of the plurality of memory access channels based upon the multilayer lookup operation is disclosed.

Lookup mechanism based on link layer semantics

In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

Multi-core multi-thread processor

A network system which includes a plurality of separate processing entities, an input output bus, and a network interface unit shared among the plurality of separate processing entities is disclosed. The network interface unit is coupled to the plurality of separate processing entities via the input output bus. The network interface unit has a plurality of memory access channels and each memory access channel is assigned to one processing entity.

System for providing virtualization of network interfaces at various layers

A rule management system and methods are disclosed. A rule management system includes a processor and an interface for receiving data comprising a plurality of data fields. The processor includes in a data structure nodes corresponding to combinations of first and second data field values. The data structure includes a node for each combination of first and second data field values for which there exists at least one rule and does not include at least one node corresponding to at least one combination of first and second data field values for which there does not exist a rule. The processor associates rules with each node of the data structure. A node and an associated set of rules for processing a data packet may be identified by determining first and second indices into the data structure that correspond to first and second data field values of the received data packet.

Efficient ACL lookup algorithms

A network system includes a network interface unit operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. The asymmetrical data processing partitions are scalable by adding additional processing entities.

Asymmetrical data processing partition

A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

Growing community of inventors

Cupertino, CA, United States of America

Michael K Wong