Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Michael K Traynor

Bryan D Hornung

Michael L Ziegler

Gregory S Palmer

David N Goldberg

A method of error protection. In one embodiment, the method of error protection consists of detecting an error during communication between nodes in a network. The nodes are separated by a link in the network. Further communication between the nodes is blocked in response to the detected error. The blocked communication is then unblocked, provided the communicating nodes have resolved the detected error. The unblocking of communication re-enables communication between the nodes.

Method and apparatus for supporting multiple independent failure domains

In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.

System and method for dynamically updating memory address mappings

A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache memories associated with multiple cache modules, such as a CPU or an I/O device, typically use a cache coherency protocol to ensure that the cache memories remain consistent with each other and with main memory. Popular cache coherency protocols usually include an INVALIDATE transaction that signals cache memories to invalidate a cache line associated with the address contained in the transaction. A TLB in accordance with the present invention will observe the physical address contained in an INVALIDATE request and determine whether address lies within the page table. If it does, the physical address into the page table will be converted into a virtual page number. The TLB will then be accessed to see if the TLB contains an entry for the virtual page number. If it does, that entry is purged from the TLB. By piggy-backing TLB purges on top of cache coherency transactions, the latency involved with software-based TLB purge operations of the prior art is eliminated. Furthermore, the complexity of the software required to implement the virtual memory scheme is reduced greatly because TLB purge operations are now handled by hardware.

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San Jose, CA, United States of America

Michael K Traynor