Inmos Limited

Michael K Thompson

Richard N Campbell

Howard Charles Nicholls

Michael John Norrington

Elizabeth Ann Smith

Jonathan Edwards

Robert P Haase

A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.

Semiconductor devices and fabrication thereof

Semiconductor device with a tungsten contact

In a semiconductor polycide resistive element having a first region of polysilicon of one conductivity type and second regions of polysilicon of opposite conductivity type, with silicide overlying the polysilicon but not the first region, the edges of the silicide are spaced apart from the boundaries between the opposite conductivity types.

Semiconductor element incorporating a resistive device

Method of fabricating a tungsten contact

A method of fabricating a polycide semiconductor element in which a lift-off mask is formed on a first region of a layer of polysilicon. A first dopant is implanted into second regions of the polysilicon which are adjacent the first region, the first region being masked from implantation by the lift-off mask. A layer of silicide is forced over the implanted regions and the lift-off mask and then the lift-off mask and the respective part of the layer of silicide which is deposited thereover are removed thereby to expose the first region. The method may be used to fabricate a resistive device in a polycide semiconductor element. There is also disclosed a semiconductor element, e.g. a resistive device, made by the method.

Semiconductor element and manufacture thereof

A method of fabricating a MOSFET wherein sidewall spacers are provided adjacent the gate of the MOSFET, the method including the steps of providing an insulating layer which extends over the source, drain and gate of the MOSFET and which acts as an impurity diffusion barrier; and forming on the insulating layer sidewall spacers which are composed of an insulating material.

MOSFET and fabrication method

In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

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Newport, United Kingdom

Michael K Thompson