Advanced Micro Devices Corporation

Advance Micro Devices, Inc.

Other

Globalfoundries Inc.

Michael K Templeton

Bharath Rangarajan

Bhanwar Singh

Ramkumar Subramanian

Sanjay K Yedur

Khoi A Phan

Kathleen R Early

Christopher F Lyons

Bryan K Choo

Maria Chow Chan

Nicholas H Tripsas

Arvind Halliyal

Mark S Chang

Hao Fang

Ursula Q Quinto

Angela Tai Hui

Tuan Duc Pham

Subhash Gupta

John JianShi Wang

Marina V Plat

King Wai Kelwin Ko

Mark T Ramsbey

Yu Nan Sun

Yowjuang William Liu

Lu You

Chi K Chang

Unsoon Kim

Yider Wu

Jeff P Erhardt

Masaaki Higashitani

Cristina Cheung

Terry Manchester

The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is patterned, a coating of a second material is provided thereover. The uppermost layer of the second coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.

Inverse resist coating process

The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Re-circulation and reuse of dummy-dispensed resist

A system and method is provided for monitoring and controlling the contaminant particle count contained in an aerosol during a photoresist coating and/or development process of a semiconductor. The monitoring system monitors the contaminate particle count present in the environment of the photoresist coating and/or development process, such as in a process chamber or a cup, enclosing the wafer during the process. The present invention employs in situ laser scattering or laser doppler anemometry techniques to detect the particle count level in the chamber or cup. A plurality of lasers and detectors can be positioned at different heights in or outside of a chamber or cup to facilitate detecting particles at different height levels. A laser could be used in conjunction with mirrors to provide a similar measurement. The particle count level can be used to compare with the defect level, so that it can be determined if a cleaner environment and/or process should be implemented.

In situ particle monitoring for defect reduction

A system for performing inventory control for wafers, unpackaged integrated circuits and packaged integrated circuits is provided. The system includes barcode readers, sorters and transporters operable to locate and relocate wafers, unpackaged circuits and packaged circuits. The system further includes a feedback system for feeding back information generated by the barcode readers, sorters, transporters and/or manufacturing devices associated with the wafers, unpackaged circuits and packaged circuits. The system further provides for generating Electronic Data Interchange (EDI) data that can be transmitted to wafer suppliers and employed in controlling wafer ordering, purchasing, processing and returning.

Barcode marking of wafer products for inventory control

One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

Dual layer patterning scheme to make dual damascene

The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features.

Growing copper vias or lines within a patterned resist using a copper seed layer

Resist coated wafers are rapidly and uniformly cooled by a fluid that has been cooled through the Joule-Thompson effect. Fluid from a high pressure reservoir is vented into a chamber that contains the substrates. By varying the pressure difference between the reservoir and the chamber, the temperature of the cooling fluid entering the chamber can be controlled. By also controlling the flow rate through the chamber, the average temperature difference between the fluid in the chamber and the substrates may be limited, whereby more uniform cooling is obtained. While the chamber pressure is lower than that in the high pressure reservoir, the chamber pressure may still be substantially greater than atmospheric. An elevated chamber pressure raises the specific heat and residence time of the fluid in the chamber, which also promotes uniform cooling.

System for rapidly and uniformly cooling resist

One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.

Systems and methods to determine seed layer thickness of trench sidewalls

A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin tracks. The system further includes one or more maintenance systems that schedule routine and/or special maintenance based on analysis of the diagnostic information. An alternative aspect of the system further includes one or more control information systems that generate of feedback control information employed in adapting the processes performed by the spin track.

System for monitoring and analyzing diagnostic data of spin tracks

According to one aspect of the present invention, pinhole defects in resist coatings are repaired by heating the resist briefly to induce the resist to flow and fill pinholes. The resist is brought to a temperature at or above that at which the resist flows for long enough to permit the resist to flow and fill pinhole defects, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the pinhole repair process. The entire patterned resist may be heated at once, or it may be heated one portion at a time. The application of heat may optionally be limited to locations where pinhole defects are found. By means of the invention, very thin patterned resist coatings free from pinhole defects may be obtained.

Pinhole defect repair by resist flow

A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. A differential voltage is applied to the developer plate and the wafer causing an electric field to be formed in the gap. Transportation of negatively charge photoresist material is facilitated by exposure to the electric field during the development process.

Parallel plate development with the application of a differential voltage

A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.

System and method for active control of BPSG deposition

A system and method is provided that facilitates the uniform development of a pattern on a photoresist material layer using a developer. The present invention accomplishes this end by considering the acid-base relationship of the photoresist material and developer and monitoring the development of water formed in the development process. Typically, photoresist material is purchased or manufactured with known concentrations of resin and photoacid generator. Therefore, by monitoring the development of water in the development process, the present invention can measure the acid consumption in the development process. The present invention can then utilize this information in optimizing the developer volume, developer concentration and developer time to improve the quality of the developed image pattern on the photoresist material layer.

Apparatus of monitoring and optimizing the development of a photoresist material

An in-line system and method for determining T-top gate dimensions is provided. The system comprises a wafer structure undergoing a T-top gate formation process; a scatterometry system coupled to the formation process for directing light at and collecting reflected light from the wafer structure; a signature store; a T-top gate formation analysis system coupled to the scatterometry system and to the signature store for determining the T-top gate dimensions; and a feedback control system coupled to the T-top gate formation analysis system for optimizing T-top gate formation. The method comprises providing a wafer structure having a T-top gate formed thereon; generating a signature associated with the T-top gate; comparing the generated signature with a signature store to determine the dimensions of the T-top gate; if the dimensions of the T-top gate are not within a pre-determined acceptable range, then adjusting T-top gate process parameters using feedback control.

System and method for process monitoring of polysilicon etch

A system for detecting voids in an ILD layer is provided. The system includes one or more light sources, each light source directing light to respective portions of the ILD layer. Light reflected from the respective portions is collected by a measuring system that processes the collected light. The collected light is indicative of the presence of voids in the respective portions of the ILD layer. The measuring system provides ILD layer void related data to a processor that determines whether voids exist in the respective portions of the ILD layer. The processor selectively marks the ILD layer portions to facilitate further processing and/or destruction of the IC with the ILD layer voids.

Growing community of inventors

Atherton, CA, United States of America

Michael K Templeton