National Semiconductor Corporation

Michael K Mayes

Sing W Chin

An n-bit analog-to-digital converter system, where n is a positive integer, includes a ratioed reference voltage generator that uses a reference voltage V.sub.ref. The reference voltage generator includes a voltage selector having a plurality of voltage selector inputs and a plurality of voltage selector outputs for applying a first voltage to a corresponding voltage selector output during a time period .phi..sub.1 and for applying a second voltage to a corresponding voltage selector output during a following time period .phi..sub.2. The voltage applied to one voltage selector output during any time period is not necessarily the same as the voltage applied to another voltage selector output. The reference voltage generator further includes an amplifier having a plurality of inputs and a differential voltage output and a plurality of sets of capacitances. Each set of capacitances couples an associated one of the voltage selector outputs to an associated one of the inputs of the amplifier and has a value such that the electrical combination of the voltages and capacitances provides a voltage level of .+-.V.sub.ref /m, where m is any desired number, at the differential output of the amplifier.

N-bit analog-to-digital converter having ratioed reference voltage

A novel ratioed reference voltage circuit is taught which enables positive and negative output voltages as a ratio of a given reference voltage. The desired ratio is established by capacitor ratios. During the operation of the circuit, positive and negative ratioed output voltages are provided at various points in time which are not necessarily very accurate due to component mismatches and the like. However, the average of the positive ratioed reference voltage during two different periods of time is a highly accurate positive ratioed reference voltage due to error cancellation. Similarly, the average of the negative ratioed reference voltage during two different periods of time is a highly accurate negative ratioed reference voltage due to error cancellation.

Ratioed reference voltage generation using self-correcting capacitor

An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying .+-.Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured. In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, for example, capacitor value voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit stages, and using these voltage coefficients to further adjust the digital output word, providing an even more accurate digital representation of the analog input signal being measured.

Pipelined analog-to-digital converter with curvefit digital correction

A method and apparatus for providing a single digital simulation of a circuit with analog and digital components. A netlist characterizing a circuit with analog and digital components is utilized. The netlist defines each component in the circuit and its interconnections. The netlist is conveyed to a digital simulator which includes an expanded cell library. The cell library defines analog components in a digital manner. The digitally defined analog components process analog signals which are simulated as arrays of binary values, termed vector voltages. The vector voltages may be combined, mathematically or logically, with other vector voltages to produce binary signals suitable as inputs to digital circuit elements. Regardless of the complexity of the circuit, and despite the fact that both analog and digital components are present, a single integrated digital simulation of the entire circuit is rapidly executed by utilizing digital models of the analog components.

Digital circuit simulation of analog/digital circuits

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a 'parallel successive approximation register' circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value.

Multistep analog-to-digital converter with successive approximation

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value. In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.

Multistep analog-to-digital converter with embedded correction data

In a sample and hold circuit comprising a plurality of serially connected comparators wherein each comparator has a feedback switch coupled between an input terminal and an output terminal of the comparator, and wherein data is held on high impedance capacitive nodes, when the series of feedback switches turn off, a capacitor is coupled across a current switching transistor which has a control terminal coupled for receiving a feedback switch control signal. When the feedback switch control signal undergoes a transition, the capacitor causes a voltage to ramp up or down. A current limiting transistor having a control terminal coupled for receiving a delay control signal is coupled in series with the current switching transistor for controlling the rate of current flow through the current switching transistor in accordance with the magnitude of the delay control signal. The voltage at the capacitor is coupled to a compare circuit having an output signal which changes state when the voltage at the capacitor passes a threshold value. This output signal functions as a delayed switching signal for delaying the turnoff of subsequent feedback switches in the series.

Method and apparatus for reducing the effects of feedback switch charge

A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning the controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.

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San Jose, CA, United States of America

Michael K Mayes