Cirrus Logic Inc.

Apple Inc.

S3 Incorporated, Inc.

Appian Graphics Corp.

Michael K Larson

Daniel P Wilde

John Kenneth Stauffer

Patrick A Harkin

Timothy J McDonald

Charlie Lao

Gautam P Vaswani

Mark Alan Einkauf

Tom C Martyn

Tom A Dye

According to one aspect of the invention, a query request is received from a client application at a multithreaded graphics framework. The multithreaded graphics framework including a first thread configured to place graphics commands from the client application into a command queue and a second thread configured to dispatch the graphics commands from the command queue to a graphics processing unit (GPU) for execution. In response to the query request, the first thread is configured to store query information of the query request in a query block of memory that is separated from the command queue and notifying the second thread. In response to the notification, the second thread is configured to issue a query command to the GPU based on the query information retrieved from the query block, prior to dispatching remaining graphics commands pending in the command queue.

Fast queries in a multithreaded queue of a graphics system

Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Methods and systems for processing objects in memory

A multi-monitor computer system (,) includes a configuration address space (,) for software driven initialization and configuration. A monitor synchronization method (,) of this invention includes temporarily remapping multiple graphics chips (,) to a same base address (,) so that attempts to write to a memory mapped register on one of the graphics chips, also writes the same register on the other graphics chips. Once the addresses are remapped, writing chip enabling data to an enabling register on one of the graphics chips causes enabling data to be written to all graphics chips at the same time, thereby synchronizing the vertical and horizontal sync signals generated by the graphics chips. Finally, remapping the graphics chips to their original base memory addresses allows the computer system to resume selective addressing of the graphics chips, which now provide synchronized vertical and horizontal sync signals to their respective monitors.

Computer system with multiple monitor control signal synchronization apparatus and method

A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

Circuits systems and methods for managing data requests between memory

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes selective pixel data fillers for writing either X or Y position pixel data to the internal SRAM devices. By selectively storing either X or Y position pixel data, the graphics processor is able to perform bit-block data transfers (blts) of pixel data to the internal SRAM thereby efficiently utilizing the local bandwidth of the internal SRAM.

Opposing directional fill calculators in a graphics processor

A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.

Host DMA through subsystem XY processing

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates from a first clock domain a display list which includes poly parameter data for rendering the graphics primitives. A graphics processor which includes internal fetch and store unit stores and processes the polygon parameter data in a second clock domain different from the first clock domain. To ensure the complete processing of polygon data from the first clock domain in the second clock domain, the graphics processor includes a polygon data tracking logic for tracking the flow of the polygon data in the graphics processor. The polygon data tracking logic includes an up/down counter which up counts polygon data fetched in the graphics processor and down counts the polygon data when the polygon data is processed in the graphics processor.

Tracking of graphics polygon data from different clock domains in a

A texture value determining (TVD) circuit approximates non-homogenous 2nd order perspective texture mapping to provide texture for a polygon using linear interpolation and input parameters. The TVD circuit of the present invention includes a vertical walk subcircuit and an orthogonal walk subcircuit. The vertical walk subcircuit determines texture coordinates, u(a.sub.0,n) and v(a.sub.0,n) that represent the pixels along a vertical main slop of a triangle polygon. The orthogonal walk subcircuit determines texture coordinates, u(a.sub.m,n) and v(a.sub.m,n), for orthogonally walked polygon coordinate positions for which m&gt;0. The orthogonally walked coordinate positions represent individual scan lines. The vertical walk subcircuit of the TVD circuit includes adders, latches, and accumulators. Each element of the vertical walk subcircuit receives a vertical main slope clock (n-clock) signal. An output of the vertical walk subsystem is computed based on the relationship,

Circuit for determining non-homogenous second order perspective texture

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a pixel data striping control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic stripes the access into separate blocks of pixel data for each access which are then simultaneously accessed during a single data request cycle. By striping pixel data accessed, the graphics processor is able to execute a single pixel dat request without crossing a X boundary even if the original pixel data being accessed spans multiple tiles in the memory device.

Pixel data X striping in a graphics processor

A graphics system includes a graphics processor for rendering graphics primitives with a display list. A host processor generates a display list which includes a command format for loading the display list into a register file. The graphics processor includes logic to encode and decode the command register to sequentially load the display list into the register file without a physical reference to the register being loaded. The command register may also be programmed to allow the graphics processor to randomly load the register file thereby shortening the processing of the display list and allowing the display list to be written during a burst cycle mode of bus operation.

Method and apparatus for programming a graphics subsystem register set

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Method and apparatus for automatically controlling the destination of a

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a memory control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic divides the access into two separate accesses which are then non-sequentially accessed during a single data request cycle. By non-sequentially fetching and storing data, the graphics processor is able to execute a single X crossing for multiple Y scan-line operations to fetch or store data internally.

Non-sequential fetch and store of XY pixel data in a graphics processor

A graphics system includes a graphics controller for rendering polygons with a minimum number of steps and registers. The graphics controller includes a register file for receiving initial parameters for the polygon from a host. The graphics controller also includes a polygon engine for loading parameters from the register file and using these parameters to generate a starting X value for each scan line and a width value for each scan line to permit efficient rendering of the polygon without 'edge walking' the polygon. The polygon engine includes a counter and a pair of accumulators for defining the number of orthogonal scan lines, the X start value for each scan line, and the width of each scan.

System and method of rendering polygons into a pixel grid

A method for computing input parameters used in a non-homogeneous second order perspective texture mapping process using interpolation. The present invention receives a polygon primitive (e.g., triangle) including screen display coordinates and texture map coordinates for each vertex (vmin, vmid, and vmax). Based on vertex information including perspective weights, w, screen display coordinates and texture map coordinates are determined for midpoints (i and j) of the two triangle slopes opposite the triangle's major slope. Based on a determined quadratic equation of the triangle's major slope, screen coordinates and texture map coordinates are determined at several selected points (e.g., imain, jmain, and midmain) along the major slope that corresponds to the i, j, and vmid points. From these values, quadratic coefficients a1, a2, and du.sub.-- ortho.sub.-- add are computed and also quadratic coefficients b1, b2 and dv.sub.-- ortho.sub.-- add are computed. The above values, parameters u.sub.-- main, du.sub.-- main (change in u over change in y), d2u.sub.-- main (change in .DELTA.u over change in .DELTA.y), du.sub.-- ortho (change in u over change in x), d2u.sub.-- ortho (change in .DELTA.u over change in .DELTA.x), v.sub.-- main, dv.sub.-- main (change in v over change in y), d2v.sub.-- main (change in .DELTA.v over change in .DELTA.y), dv.sub.-- ortho (change in v over change in x), and d2v.sub.-- ortho (change in .DELTA.v over change in .DELTA.x) are computed and forwarded to a non-homogenous second order perspective texture mapping process using interpolation. The above texture mapping process is extremely efficient as it is free of division operations during the interpolation.

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Kirkland, WA, United States of America

Michael K Larson