International Business Machines Corporation

Globalfoundries Inc.

Michael K Gschwind

Valentina Salapura

Chung-Lung K Shum

Timothy John Slegel

Eric M Schwarz

Jonathan D Bradbury

Fadi Y Busaba

Maged M Michael

Christian Jacobi

Giles R Frazier

Harold Wade Cain, Iii

Ulrich Weigand

Brett Olsson

Dan F Greiner

Anthony Saporito

Anthony J Bybell

John-David Wellman

Charles W Gainey, Jr

William Jon Schmidt

Alexandre E Eichenberger

Erik Richter Altman

Sumedh Wasudeo Sathaye

Alan G Gara

Brian William Thompto

Kathryn Mary O'Brien

Bradly George Frey

John Kevin O'Brien

Jose Eduardo Moreira

John A Gunnels

Balaram Sinharoy

Robert K Montoye

Jude A Rivers

Steven Jay Munroe

Harm Peter Hofstee

Ravi Nair

Bruce Martin Fleischer

James Allan Kahle

Chen-Yong Cher

Victor V Zyuban

Robert J Blainey

Markus Kaltenbach

Jentje Leenstra

Charles Ray Johns

David Arnold Luick

Bartholomew Blaner

Martin Ohmacht

Zehra Noman Sura

Peng Wu

John Kevin Patrick O'Brien

Dong Chen

Paul William Coteus

Lisa Cranton Heller

Damian Leo Osisek

Pradip Bose

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Naresh Nayar

Todd Edward Takken

Robert William Wisniewski

Thomas M Gooding

Michael Norman Day

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

Thomas Winters Fox

Raul Esteban Silvera

Barry Marshall Trager

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Daniel Arthur Prener

Gerard Vincent Kopcsay

Sarbajit Kumar Rakshit

Clifford A Pickover

Maja Vukovic

Alper Buyuktosunoglu

Brian E Smith

Eric Vance Kline

Silvia Melitta Mueller

Philip George Emma

Ruchi Mahindru

Mark Richard Nutter

Vijayalakshmi Srinivasan

Hans Mikael Jacobson

Richard James Eickemeyer

Masakazu Suzuoki

Barry L Minor

Stanley Everett Schuster

Anthony Cappa Spielberg

Jonathan R Fry

James Xenidis

John Scott Houston

Fred Gehrung Gustavson

A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to be examined and a result location. The register includes a plurality of elements. In execution, the machine instruction counts a number of contiguous elements of the plurality of elements of the register having a particular value in a selected location within the contiguous elements. Other locations within the contiguous elements are ignored for the counting. The counting provides a count placed in the result location.

Instructions to count a number of contiguous register elements having specific values in a selected location

A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Memory access request for a memory protocol

Portions of configuration state registers in-memory. An instruction is obtained, and a determination is made that the instruction accesses a configuration state register. A portion of the configuration state register is in-memory and another portion of the configuration state register is in-processor. Processing associated with the configuration state register is performed. The performing processing is based on a type of access and whether the portion or the other portion is being accessed.

Portions of configuration state registers in-memory

Aspects of branch prediction are suppressed for branch instructions executing in a transaction, of a transactional memory environment, that is a re-execution of a previously aborted transaction.

Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction

A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.

Concurrent prediction of branch addresses and update of register contents

A determination is made that a unit of memory that provides storage for one or more in-memory configuration state registers is to be pinned in a system that includes a guest operating system and one or more hosts at one or more host levels. Based on determining that the unit of memory is to be pinned, at least one host of the one or more hosts is notified that the unit of memory is to be pinned.

Automatic pinning of units of memory

An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Latent modification instruction for substituting functionality of instructions during transactional execution

Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.

Selective suppression of instruction translation lookaside buffer (ITLB) access

A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

Indicator-based prioritization of transactions

A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.

Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence

Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.

Selective suppression of instruction cache-related directory access

Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module, a pointer value for a reference data structure is determined. The pointer value is stored in a reference data structure tracking structure, and used to access a variable value for a variable of the module.

Initializing a data structure for use in predicting table of contents pointer values

A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Set table of contents (TOC) register instruction

Growing community of inventors

Chappaqua, NY, United States of America

Michael K Gschwind