Micron Technology Incorporated

Hewlett-packard Development Company, L.P.

Chiaro Networks Ltd

Convey Computer

Michael K Dugan

Tony M Brewer

J Michael Andrewartha

William D O'Leary

Gary Belgrave Gostin

Bryan D Hornung

Gregory S Palmer

Curtis R McAllister

Christopher A Baronne

Jim Kleiner

John M Wastlick

Paul F Vogel

Mark A Heap

Henry Yu

Terry C Huang

Various examples are directed to an arrangement comprising a first hardware compute element and a hardware balancer element. The first hardware compute element may send a first request message to a hardware balancer element. The first request message may describe a processing task. The hardware balancer element may send a second request message towards a second hardware compute element for executing the processing task and send to the first compute element a first reply message in reply to the first request message. After sending the first reply message, the hardware balancer element may receive a first completion request message indicating that the processing task is assigned and send, to the first hardware computing element, a second completion request message, the second completion request message indicating that the processing task is assigned.

Methods and systems for communications between hardware components

A system includes a host device having a first buffer with ordered data. An accelerator device has a data movement processor and a reordering buffer. A multiple-channel interface couples the host device and the data movement processor of the accelerator device. The data movement processor is configured to issue a read command for a portion of the ordered data. In coordination with issuing the read command, an entry of the reordering buffer is allocated. A transaction identifier for the read command is allocated. Unordered responses are received from the host device via the multiple-channel interface. The responses include respective portions of the ordered data and a respective transaction identifier. The responses are reordered in the reordering buffer based on the respective transaction identifiers and the allocated entry of the reordering buffer.

Access request reordering across a multiple-channel interface for memory-based communication queues

A system includes a memory device and a command manager configured to reorder read requests. The command manager is configured to receive a read response associated with a transaction identifier for the read request. A free list entry for the read request is allocated from a free list. The free list entry is associated with a transaction identifier of the read request. A tail index of a reordering queue is written to a remapping queue based on the free list entry. The tail index is configured to provide a write address of the reordering queue that is allocated for the read request. A read response associated with the transaction identifier for the read request is received. The read response is written to the allocated entry of the reordering queue.

Access request reordering for memory-based communication queues

Host and accelerator devices can be coupled using various interfaces, such as Compute Express Link (CXL). In an example, user applications can have protected access to a shared set of control parameters for different queues. A protocol can allow an application to use a unique memory page at the accelerator device through which the application can access control parameters, such as can be used to control memory-based communication queues or other queues. In an example, there can be multiple sets of control parameters in a single memory page. The protocol can allow views of the single memory page from respective different application processes. In an example, the protocol can include or use an access check to detect and handle unauthorized accesses to particular parameters.

Control parameter address virtualization

A system includes a host device, a memory device, and a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device. The command manager is further configured to receive a command response associated with a transaction identifier for each command. An index value for the command is written to a reordering queue. In response to a command response write for the command response, the index value from the reordering queue is read. The index value is written in an index update queue. A network write index update message is transmitted.

Reducing index update messages for memory-based communication queues

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Multiple data channel memory module architecture

The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.

Systems and methods for scheduling memory requests utilizing multi-level arbitration

Hardware interconnected around multiple packet forwarding engines prepends sequence numbers to packets going into multiple forwarding engines through parallel paths, After processing by the multiple forwarding engines, packets are reordered using queues and a packet ordering mechanism, such that the sequence numbers are put back into their original prepended order. Exception packets flowing through the forwarding engines do not follow a conventional fast path, but are processed off-line and emerge from the forwarding engines out of order relative to fast path packets. These exception packets are marked, such that after they exit the forwarding engines, they are ordered among themselves independent of conventional fast path packets. Viewed externally, all exception packets are ordered across all multiple forwarding engines independent of the fast path packets.

System and method for router packet control and ordering

An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

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Richardson, TX, United States of America

Michael K Dugan