Sonics, Incorporated

Cadence Design Systems, Inc.

Center for Deep Learning in Electronics Manufacturing, Inc.

D2s, Inc.

Sonic Corporation

Cadance Design Systems, Inc.

Michael Jude Meyer

Wolf-Dietrich Weber

Drew Eric Wingard

Kamil Synek

Chien-Chun Chou

Jay S Tomlinson

Yosinori Watanabe

Ajay Baranwal

Thang Nguyen

Scott Carlton Evans

Nabil Masri

Walter J Ghijsen

Geert Paul Rosseel

Jeffrey Allen Ebert

David Van Campenhout

Thomas Wayne O'Connell

Akira Fujimura

Luciano Lavagno

Stephen W Hamilton

Patrick Charles McGeer

Alex Kondratyev

Suhas Pillai

Felice Balarin

Patrick Scaglia

Lisa A Robinson

Szu-Tsung Cheng

Sherry Solden

Michael T Y McNamara

Joseph Harwood

Abhinav Tallapally

Viorica Simion

Methods for compressing shape data for a set of electronic designs include inputting a set of shape data, where the shape data comprises mask designs. A convolutional autoencoder encodes the set of shape data, where the encoding compresses the set of shape data to produce a set of encoded shape data. The convolutional autoencoder is tuned for increased accuracy of the set of encoded shape data based on design rules for the set of shape data. The convolutional autoencoder comprises a set of parameters comprising weights, and the convolutional autoencoder has been trained to determine what information to keep based on the weights.

Methods and systems for compressing shape data for electronic designs

Methods for fracturing or mask data preparation are disclosed in which a set of single-beam charged particle beam shots is input; a calculated image is calculated using a neural network, from the set of single-beam charged particle beam shots; and a set of multi-beam shots is generated based on the calculated image, to convert the set of single-beam charged particle beam shots to the set of multi-beam shots which will produce a surface image on the surface. Methods for training a neural network include inputting a set of single-beam charged particle beam shots; calculating a set of calculated images using the set of single-beam charged particle beam shots; and training the neural network with the set of calculated images.

Methods and systems for forming a pattern on a surface using multi-beam charged particle beam lithography

Methods for compressing shape data for a set of electronic designs include inputting a set of shape data, where the shape data represents a set of shapes for a device fabrication process. A convolutional autoencoder is used on the set of shape data, the convolutional autoencoder having a pre-determined set of convolution layers including a kernel size and filter size for each convolution layer. The set of shape data is encoded to compress the set of shape data, using the pre-determined set of convolution layers of the convolutional autoencoder, to create a set of encoded shape data. The set of shape data comprises an SEM image, and the encoded set of shape data identifies a mask defect.

Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

Annotations to identify objects in design generated by high level synthesis (HLS)

In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.

Methods, systems, and apparatus for reliability synthesis

Various methods and apparatuses are described for an arbitration unit that implements a round robin policy. Each requesting device has an equal chance of accessing a shared resource based upon a current request priority assigned to that requesting device. The arbitration unit includes at least a state block that includes a plurality of state registers. The plurality at least includes a first state register for a first unordered pair of requesting devices, a second state register for a second unordered pair of requesting devices, and a third state register for a third unordered pair of requesting devices.

Method and apparatus for round robin resource arbitration with a fast request to grant response

A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

System and method for incremental synthesis

Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a second burst capability. The supported burst features of the second burst capability differ from the supported burst features of the first burst capability. The communication system also comprises an agent coupled to the initiator core, which comprises logic to compute target-dependent burst support information across multiple groups of potential targets at the same time. The logic then selects the correct target-dependent information based upon a resulting address decode for the target selection.

Various methods and apparatuses for width and burst conversion

Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

Various methods and apparatus for width and burst conversion

Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.

Method and apparatus for optimizing distributed multiplexed bus interconnects

Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Composing on-chip interconnects with configurable interfaces

A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration options, capturing the specific core configuration through manual entry or through the use of a Graphical User Interface, and providing for software that combines the source description of the core with the configuration data to generate the core with an optimally configured logic and circuit interface.

Logic system with configurable interface

A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

On-chip inter-network performance optimization using configurable performance parameters

A method and apparatus for error handling in networks have been described. The method configures a plurality of cores, wherein each core is connected with and associated with each of one of a plurality of initiators. The method further connects one or more of the initiators to a network. Next, one or more of the initiators determine an error in one or more of the cores and communicate the error.

Method and apparatus for error handling in networks

A method and apparatus for optimizing distributed multiplexed bus interconnects are described. The multiplexed bus interconnect contains one or more multiplexers to route signals through the bus interconnect. An amount of signaling wiring present within a distributed multiplexed bus interconnect is optimized by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the multiplexed bus interconnect transmits or receives signals from the distributed multiplexed bus interconnect.

Growing community of inventors

Palo Alto, CA, United States of America

Michael Jude Meyer