Other

Adaptec, Inc.

Dot Hill Systems Corporation

Hynix Semiconductor Inc.

Michael Joseph Peters

Patrick R Bashford

Rex Weldon Vedder

Bradford Edwin Golson

Gene Maine

Donald N Allingham

Bradley J Wright

James R Klobcar

David M Musolf

Richard L Collins

A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.

Memory calibration method and apparatus for power reduction during flash operation

A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.

Buffer management method and apparatus for power reduction during flush operation

A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.

Sparse byte enable indicator for high speed memory access arbitration method and apparatus

The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device. The bridge control circuitry is further arranged to receive a first data transfer request from a selected master device for transferring data between the selected master device and a selected slave device. The bridge control circuitry issues a second data transfer request to the selected slave device for transferring the data. The bridge control circuitry receives the requested data from the source device and stores the received data in the prefetch buffer. The bridge control circuitry transfers the stored data from the prefetch buffer to the destination device when the prefetch buffer receives and stores data size that correspond to the prefetch size stored in a prefetch control register associated with the selected master device.

Bridge device for transferring data using master-specific prefetch sizes

A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin. The model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations.

Integrated circuit I/O pad cell modeling

A multiple client memory arbitration system supporting simultaneous arbitration access to a local cache memory and a remote cache memory for mirrored write operations to both the local cache memory and the remote cache memory by one of a local arbitration device or a remote cache memory at a time. The enhanced arbitration system includes active/active failover control by a surviving one of the local arbitration device or the remote arbitration device that have participated in the mirrored write operations between the respective local cache memory and the remote cache memory.

Fault tolerant multiple client memory arbitration system capable of

A multiple client memory arbitration system to arbitrate client access to a single cache memory in an I/O controller device having at least one internal client in addition to the possibility of at least one external client. The system includes an arbitrator, the ability to determine a configuration type for the I/O controller device selected from a group of configuration types consisting of an unknown device configuration, single device configuration, multiple device master configuration, and multiple device slave configuration, the ability to configure the arbitration device based on a configuration type, the ability to refresh the cache memory independent of the configuration type, and the ability to execute failover control of the cache memory in an event of an I/O controller device failure in a multiple arbitration device configuration.

Multiple client memory arbitration system capable of operating multiple

A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation monitor executes unobtrusively as part of the logic simulation to monitor the logic simulation's real time signal activity including contention checks, output strobe margins, and ATE compatibility checks, in addition to extracting the appropriate signal response or vector resulting from a given stimulus. The simulation monitor comprises at least one simulation monitor code block generated from a combination of values from an integrated circuit parameter file and at least one code block template. Output from the simulation monitor includes a report of the contention errors and input signal errors, and a test vector set comprised of the input test stimulus set used with the logic simulation and the stimulus responses resulting from the logic simulation all in an ATE compatible and ready to use format.

Integrated circuit test stimulus verification and vector extraction

A protective cover (22) for disposition over a patient bearing structure, such as a gurney (10) comprises a liquid impervious membrane having a liquid absorbent pad (24) thereon. The cover (22) minimizes transportation of potentially infectious biological fluids to the gurney (10). The cover (22) is further provided with triangular corner flaps (46), (48), (50), and (52), which allow railings (14), (16), (18), and (20) to be raised or lowered without requiring the cover (22) to be unfastened.

Gurney with protective cover

An intubation instrument has an abraded and adsorbent sheath that is telescoped both internally and externally of a tube. The sheath is provided with a handle to facilitate retraction thereof as the tube is inserted into a body cavity, thereby minimizing transportation of pathogens into the body.

Method of using an intubation instrument

A catheter comprises a relatively stiff drainage tube having an inflatable sheath telescoped thereover. The sheath is inflated after insertion of the tube and sheath into the urethra of a patient. The sheath has a plurality of circumferentially spaced relative thin sections that form circumferentially spaced catheter retention balloons at the insertion end of said tube when said sheath is inflated thereby to facilitate complete drainage of the bladder.

Bladder catheter

An expandable intravenous catheter for the infusion of fluids into a blood vessel comprises a helically wound tube having a diameter that can be varied from a normal minimum diameter to a relatively larger diameter by axial movement of the ends of the tube relative to each other, after insertion of the catheter into the blood vessel.

Intravenous catheter

A system for introducing a nasogastric tube into the stomach of a patient comprises a digestible weight capable of being swallowed by the patient, a digestible guide string having one end attached to the weight, and a tube telescoped about the guide string for guidance thereby into the stomach of said patient.

Growing community of inventors

Fort Collins, CO, United States of America

Michael Joseph Peters