International Business Machines Corporation

Globalfoundries Inc.

Michael Joseph MacDonald

Mark P Murray

Mahadevaiyer Krishnan

Yun Yu Wang

Kirk David Peterson

Yun-Yu Wang

Donald Francis Canaperi

Eric Jeffrey White

Shai N Gozani

Michael F Lofaro

Thomas George Ference

William J Cote

Gregory Wolos

Anthony Gene Domenicucci

Kenneth John Giewont

William Francis Landers

Ahmad D Katnani

Cuc Kim Huynh

Marc P Cryan

Michael L Williams

Russell Herbert Arndt

Kenneth M Davis

Glenn Herb

James Anthony Tornello

Scott Alan Estes

Michael T Brigham

Walter E Mlynko

Bonniejean Boettcher

Michael A Cobb

Jeffrey J Brown

Edward Jack Gordon

James Hannah

Pratap Uday Ganapathy

Jochonia N Nxumalo

Kenneth A Bandy

Tim Proulx

Timothy Scott Chamberlin

Dean Allen Schaffer

Craig M Ransom

Judith A Coffin

Dimitrios Ioannou

Brian E Johnson

Jeffrey S Mekler

L Joy Somogyi

George James Slusser

Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Mitigation of hot carrier damage in field-effect transistors

Transcutaneous electrical nerve stimulation (TENS) device

A polishing inhibiting layer forming additive for a slurry, the slurry so formed, and a method of chemical mechanical polishing are disclosed. The polishing inhibiting layer is formed through application of the slurry to the surface being polished and is removable at a critical polishing pressure. The polishing inhibiting layer allows recessed or low pattern density locations to be protected until a critical polishing pressure is exceeded based on geometric and planarity considerations, rather than slurry or polishing pad considerations. With the additive, polishing rate is non-linear relative to polishing pressure in a recessed/less pattern dense location. In one embodiment, the additive has a chemical structure: [CH(CH)N(R)]M, wherein M is selected from the group consisting of: Cl, Br and I, x equals an integer between 2 and 24, and the R includes three carbon-based functional groups, each having less than eight carbon atoms.

Method of forming a polishing inhibiting layer using a slurry having an additive

A slurry containing abrasive particles, an oxidizing agent having a low static etch rate on at least one acid or salt metal, and having a pH of about 5 to about 11 is especially useful for polishing surfaces, including both metal and silicon dioxide, such as present in microelectronics, at the same or substantially the same polishing rates.

Slurry and use thereof for polishing

Slurry compositions comprising an oxidizing agent, optionally a copper corrosion inhibitor, abrasive particles; surface active agent, a service of chloride and a source of sulfate ions.

Slurry for mechanical polishing (CMP) of metals and use thereof

A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.

Method for improved fabrication of salicide structures

A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

Combined chemical mechanical polishing and reactive ion etching process

A slurry containing abrasive particles and a pH buffering component comprising at least one acid or salt thereof and at least one base is especially useful for polishing surfaces, including those used in microelectronics.

pH-buffered slurry and use thereof for polishing

Growing community of inventors

Yorktown Heights, NY, United States of America

Michael Joseph MacDonald