Lumileds Lighting U.s., LLC

Agilent Technologies, Inc.

Philips Lumileds Lighting Company LLC

Michael Joseph Ludowise

Daniel Alexander Steigerwald

Jerome Chandra Bhat

Michael Ragan Krames

Shih-Yuan Wang

Yong Qin Chen

Theodore I Kamins

Paul Scott Martin

Scott W Corzine

Michael David Camras

Frank Michael Steranka

Stephen Andrew Stockman

Pierre H Mertz

Steven A Maranowski

Fred A Kish

Yu-Chen Shen

Jonathan J Wierer, Jr

Serge Laurent Rudaz

Robert M Fletcher

Jason L Posselt

William D Collins Iii

A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.

Contacting scheme for large and small area semiconductor light emitting flip chip devices

A light emitting device includes a resonant cavity formed by a reflective metal layer and a distributed Bragg reflector. Light is extracted from the resonant cavity through the distributed Bragg reflector. A light emitting region sandwiched between a layer of first conductivity type and a layer of second conductivity type is disposed in the resonant cavity. In some embodiments, first and second contacts are formed on the same side of the resonant cavity, forming a flip chip or epitaxy up device.

Resonant cavity light emitting device

A mount for a semiconductor light emitting device includes an integrated reflector cup. The reflector cup includes a wall formed on the mount and shaped and positioned to reflect side light emitted from the light emitting device along a vertical axis of the device/mount combination. The wall may be covered by a reflective material such as a reflective metal.

Integrated reflector cup for a light emitting device mount

A light-emitting semiconductor device includes a stack of layers including an active region. The active region includes a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof. A superstrate substantially transparent to light emitted by the active region is disposed on a first side of the stack. First and second electrical contacts electrically coupled to apply a voltage across the active region are disposed on a second side of the stack opposite to the first side. In some embodiments, a larger fraction of light emitted by the active region exits the stack through the first side than through the second side. Consequently, the light-emitting semiconductor device may be advantageously mounted as a flip chip to a submount, for example.

III-Phosphide and III-Arsenide flip chip light-emitting devices

Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.

Light emitting semiconductor method and device

A structure includes semiconductor light emitting device and a wavelength converting layer. The wavelength converting layer converts a portion of the light emitted from the semiconductor light emitting device. The dominant wavelength of the combined light from the semiconductor light emitting device and the wavelength converting layer is essentially the same as the wavelength of light emitted from the device. The wavelength converting layer may emit light having a spectral luminous efficacy greater than the spectral luminous efficacy of the light emitted from the device. Thus, the structure has a higher luminous efficiency than a device without a wavelength converting layer.

Light emitting devices with enhanced luminous efficiency

In accordance with embodiments of the invention, a light emitting device includes a light emitting region and a reflective contact separated from the light emitting region by one or more layers. In a first embodiment, the separation between the light emitting region and the reflective contact is between about 0.5&#x3bb;and about 0.9&#x3bb;, where &#x3bb;is the wavelength of radiation emitted from the light emitting region in an area of the device separating the light emitting region and the reflective contact. In a second embodiment, the separation between the light emitting region and the reflective contact is between about &#x3bb;and about 1.4&#x3bb;. The light emitting region may be, for example, III-nitride, III-phosphide, or any other suitable material.

Selective placement of quantum wells in flipchip light emitting diodes for improved light extraction

A dielectric layer is formed on the mesa wall of a flip-chip LED. The dielectric layer is selected to maximize reflection of light incident at angles ranging from 10 degrees towards the substrate to 30 degrees away from the substrate. In some embodiments, the LED is a III-nitride device with a p-contact containing silver, the dielectric layer adjacent to the mesa wall is a material with a low refractive index compared to GaN, such as AlO.

Semiconductor LED flip-chip with dielectric coating on the mesa

In accordance with the invention, a light emitting device includes a substrate, a layer of first conductivity type overlying the substrate, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A plurality of vias are formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, or selective growth of the layer of second conductivity type. A set of first contacts electrically contacts the layer of first conductivity type through the vias. A second contact electrically contacts the layer of second conductivity type. In some embodiments, the area of the second contact is at least 75% of the area of the device. In some embodiments, the vias are between 2 and 100 microns wide and spaced between 5 and 1000 microns apart.

III-Phospide and III-Arsenide flip chip light-emitting devices

In accordance with the invention, a difference in index of refraction is created at the mesa wall of a III-nitride flip chip light emitting device. The step in index of refraction reflects much of the light incident on the mesa wall back into the device where it can be usefully extracted. In some embodiments, a solder wall on the submount or a high index gel coating the light emitting device and the submount creates a sealed gap between the light emitting device and the submount. The gap is filled with a material having a low index of refraction. In other embodiments, a high index material covers the substrate of the light emitting device, and a low index material fills the gap between the submount and the light emitting device.

Semiconductor LED flip-chip having low refractive index underfill

A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

Integrated circuit substrate that accommodates lattice mismatch stress

A method of forming a light-transmissive contact on a p-type Gallium nitride (GaN) layer of an optoelectronic device includes in one embodiment, introducing a selected metal in an oxidized condition, rather than oxidizing the metal only after it has been deposited on the surface of the p-type GaN layer. In some applications, the oxidized metal provides sufficient lateral conductivity to eliminate the conventional requirement of a second highly conductive contact metal, such as gold. If the second contact metal is desired, an anneal in an oxygen-free environment is performed after deposition of the second layer. The anneal causes the second metal to penetrate the oxidized metal and to fuse to the surface of the p-type GaN layer. In a second embodiment, the oxidation occurs only after at least one of the two metals is deposited on the surface of the p-type GaN layer. In one application of the second embodiment, the two metals are deposited and the oxidation occurs in an environment that includes both water vapor and oxygen gas. In an alternative application of the second embodiment, the first metallic layer is deposited and then oxidized throughout its depth. The second material, such as gold, is evaporated on the first material and a re-anneal step is performed to drive the second metal through the oxidized first metal. In any of the applications of either embodiment, a pattern of windows may be formed in the resulting contact structure or in additional layers that are formed thereon.

Method of forming transparent contacts to a p-type GaN layer

A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The first material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the second material by the first material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO,that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

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San Jose, CA, United States of America

Michael Joseph Ludowise