International Business Machines Corporation

Michael Joseph Laramie

Joseph Andrew Iadanza

Ralph David Kilmoyer

Frank Ray Keyser, Iii

Terrance John Zittritsch

Victor Paul Seidel

Scott Whitney Gould

Kim P Clinton

A programmable interconnect structure is provided whereby core regions of an integrated circuit having circuits of different functional types therein are connected. Ports are defined in a first core region along its boundary with a second core region, and port multiplexers selectively provide signals to the first core region from a variety of conductors in the second core region. In the case where a core region of a first type is placed between two core regions of a second type, a segmented bus structure is provided to preserve connectivity between the two core regions of the second type, while at the same time providing an increased number of independent signals available to the core region of the first type. In the exemplary integrated circuit disclosed herein, a field programmable gate array occupies one core region, and a field programmable memory array occupies another core region.

Interconnect structure between heterogeneous core regions in a

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Selective connectivity between memory sub-arrays and a hierarchical bit

Field programmable memory array

A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The invention is disclosed in association with a field-programmable memory array having multiple sub-arrays therein. The address units for each sub-array are provided to programmably provide address information to the wordlines of each sub-array from an initialization address bus or a functional address bus. Similarly, readhead and writehead circuits within each sub-array are also programmable to propagate data between initialization or functional data buses and the memory cells of the sub-array. The address units, readheads, and writeheads are all responsive to a dominant reset signal to reset the associated cells. An initialization select bus is disclosed for selecting a given sub-array of the multiple sub-arrays for the initialization function. A programming or configuration system for the field-programmable memory array is disclosed with additional units for operating the address and data buses, address units, readheads, writeheads, and the initialization buses.

System for implementing write, initialization, and reset in a memory

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Essex Jct., VT, United States of America

Michael Joseph Laramie