International Business Machines Corporation

Michael Joseph Genden

Dung Q Nguyen

Sundeep Chadha

David R Terry

Hung Qui Le

Brian William Thompto

Brian David Barrick

Maarten Jakob Boersma

Kurt Alan Feiste

Joshua W Bowman

Dhivya Jeganathan

Maureen Anne Delaney

Niels Fricke

Eula A Tolentino

Thao T Doan

Rokesh Jayasundar

Brian J D Barrick

Kenneth Lundy Ward

David S Walder

Salma Ayub

James Wilson Bishop

Michael Klaus Kroener

Cliff Kucharski

Jeffrey Carl Brownscheidle

Philip Lee Vitale

Nicholas R Orzol

Steven Bradford Herndon

Paul M Kennedy

Jerry Y Lu

Nasrin Sultana

Eric M Schwarz

Susan Elizabeth Eisen

Phillip G Williams

Christian Zoellin

Jentje Leenstra

Robert Alan Philhower

Salim Ahmed Shah

Tu-An T Nguyen

Mehul N Patel

John Fred Spannaus

Tharunachalam Pindicura

Rolf Bernhard Hilgendorf

Kent Li

Eula Faye Abalos Tolentino

Eula Faye A Tolentino

Nir Segev

Brian W Thomto

A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.

Routing instructions in a microprocessor

A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Instruction dispatch routing

A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.

Decoupling of conditional branches

A computer processing system is provided. The computer processing system includes a processor configured to execute a record form instruction cracked into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form instruction.

Low latency execution of floating-point record form instructions

Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Disclosed is a method for managing an issue queue for fused instructions and paired instructions in a microprocessor. The method includes dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.

Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions. A branch execution unit is provided as part of the instruction fetch unit to execute the selected conditional branch instruction, followed by dynamically updated any related non-executed instructions in the BRQ.

Prioritization protocols of conditional branch instructions

A computing system includes an issue queue and a microprocessor. The issue queue receives a fused instruction, which includes a first instruction portion fused with a second instruction portion different from the first instruction portion. The microprocessor assigns a first instruction tag (ITAG) to the first instruction portion and a second ITAG to the second instruction portion. The microprocessor determines a first bit that represents the first ITAG, inverts the first bit to determine a second bit that represents the second ITAT, and determines an availability of one or more sources of a second instruction different from the fused instruction based at least in part on the first bit or the second bit.

Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor

A processor-implemented method is provided. The processor-implemented includes reading, by a processor, an instruction stream by fetching instructions from an instruction cache of the processor. The processor then executes a branch prediction operation based on a context of the instruction stream and an index when one of the instructions includes a branch instruction. The branch prediction operation output a prediction and a context. The processor then compares the context of the instruction stream and the context from the branch prediction operation to determine whether to execute a stop fetch.

Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch

Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.

Merging status and control data in a reservation station

A computer processing system is provided. The computer processing system includes a processor configured to crack a record form FP instruction into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target FP register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form FP instruction.

A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

An apparatus for shared compare lanes for dependency wakeup in a double issue queue includes a source dependency module that determines a number of source dependencies for two instructions to be paired in a row of a double issue queue of a processor. A source dependency includes an unavailable status of a dependent source for data required by the two instructions where the data is produced by another instruction. The apparatus includes a pairing determination module that writes each of the two instructions into a separate row of the double issue queue in response to the source dependency module determining that the number of source dependencies is greater than a source dependency maximum and pairs the two instructions in one row of the double issue queue in response to the source dependency module determining that the number of source dependencies is less than or equal to the source dependency maximum.

Shared compare lanes for dependency wake up in a pair-based issue queue

Growing community of inventors

Austin, TX, United States of America

Michael Joseph Genden