International Business Machines Corporation

Michael Joseph Corrigan

Naresh Nayar

William Joseph Armstrong

Bruce Marshall Walk

Timothy Joseph Torzewski

Paul LuVerne Godtland

Gary Ross Ricard

David R Engebretsen

Cathy May

Edward John Silha

Wade Byron Ouren

Larry Wayne Loen

Richard Karl Kirkman

Joaquin Hinojosa

Glen Warren Nelson

Patrick James Christenson

Daniel Frank Moertl

Giles R Frazier

Brian Eric Bakke

Richard Loise Arndt

David Anthony Larson

Sheldon Bernard Levenstein

Stuart Zachary Jacobs

Scott Barnett Swaney

Jeffrey Douglas Brown

Scott Douglas Clark

Kent Harold Haselhorst

Thomas R Sand

Kenneth Charles Vossen

David Glenn Carlson

Troy David Armstrong

Michael Steven Faunce

John Thomas O'Quin, Ii

Timothy John Mullins

Larry William Youngren

Michael James McDermott

Diane Lacey Knipfer

Lynn Allen McMahon

Lynn Keat Chung

Jeffrey Jay Scheel

Philip Braun Winterfield

Kevin Curtis Griffin

Timothy R Marchini

Brian Eldridge Clark

Edwin C Grazier

Scott Alan Plaetzer

William Anton Brown

Richard Miles Rocheleau

Donald Arthur Morrison

Mark Gregory Manges

Thomas Richard Crowley

Mark Philip Piazza

Steven L Jones

Russell Paul VanDuine

George G Gorbatenko

Terrence James Stewart

George David Timms, Jr

Charlotte B Metzger

Robert Carl Beetcher

Erik Tkal

James E Bahr

Harris L Freeman

Arlys Jean Leitzen

Shiun Lee

David Robert Russell, Jr

James William Moran

Francis Joseph Reardon, Jr

Embodiments are provided for deferring allocation of storage for segments. The method includes receiving, at a first moment in time, a request to allocate a first segment within a memory. Information corresponding to the first segment is stored in a first entry in a hash table, and memory is allocated for the first segment. Information about the first segment is returned to an entity that requested the allocation of the first segment, where the first segment is not allocated auxiliary storage until predefined criteria are satisfied. At a second moment in time, upon receiving an indication to deallocate the first segment, memory corresponding to the first segment is deallocated, where the first segment is never allocated auxiliary storage and the first entry in the hash table is deleted.

Deferred method of allocating disk space for lightning segments

Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Register access in distributed virtual bridge environment

A soft lock mechanism controls access by multiple processes to a shared resource to make simultaneous access an unlikely event, while not necessarily preventing simultaneous access. Preferably, the soft lock contains a next_free_time field, specifying when the soft lock will next be available, and a lock_duration, specifying a sufficiently long interval for most accesses to the resource to complete. The lock is obtained by comparing the current time to next_free_time. If the current time is later than next_free_time, then the lock is obtained immediately, and next_free_time is updated to the current time plus lock_duration. If the current time is before next_free_time, then next_free_time is incremented by lock_duration, and the requesting process waits until the old next_free_time to obtain the lock. No action is required to release the lock.

Method and apparatus for reducing contention for computer system resources using soft locks

An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.

System and method for tracking the memory state of a migrating logical partition

Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

Mechanism that provides efficient multi-word load atomicity

An operating system kernel includes an attach mechanism and a detach mechanism. In addition, processes are tagged with an access attribute identifying the process as either a client process or a server process. Based on the access attribute, the operating system kernel lays out the process local address space differently depending on whether the process is a client process or a server process. A server process can 'attach' to a client process and reference all of the client process' local storage as though it were its own. The server process continues to reference its own process local storage, but in addition, it can reference the other storage, using the client process' local addresses. When access to the other storage is no longer needed, the server process can 'detach' from the client process. Once detached, the other storage can no longer be referenced.

Method, apparatus, and computer program product for accessing process local storage of another process

An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more 'hint bits' are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Selectively invalidating entries in an address translation cache

A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a 'processor compatibility register' (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

Method and apparatus for selecting the architecture level to which a processor appears to conform

A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer

An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more 'hint bits' are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

Apparatus and method for selectively invalidating entries in an address translation cache

A task synchronization mechanism operates on a global lock that is shared between processors an on local locks that are not shared between processors. The local locks are processor-specific locks. Each processor-specific lock is dedicated to a particular processor in the system. When shared access to a resource is required, a processor updates its processor-specific lock to indicate the processor is sharing the resource. Because each processor-specific lock is dedicated to a particular processor, this eliminates a significant portion of the memory bus traffic associated with all processors reading and updating the same lock. When exclusive access to a resource is required, the requesting processor waits until the count of all processor-specific locks indicate that none of these processors have a lock on the resource. Once no processor has a lock on the resource, exclusive access to the resource may be granted.

Task synchronization mechanism and method

According to the present invention, when an interrupt occurs in a computer system running an operating system, control takes a separate code path in the operating system, depending on whether the computer system is in non-partitioned mode or partitioned mode, before converging to a common mode-independent interrupt handler that services the interrupt. Along each separate code path, hardware state of the computer system which is relevant to the processing of the interrupt is changed to a consistent hardware state so that the common mode-independent interrupt handler can run properly in both modes.

Interrupt handlers used in different modes of operations

A partition manager for managing logical partitions in a computer system includes hooks to low-level operating system code in one of the logical partitions. By using the operating system code to manage the resources of a computer system, any changes that are made to the operating system are automatically reflected in the function of the partition manager. In addition, low-level functions of operating systems, which are often well-debugged and tested, can be used when generating a new partition manager, greatly simplifying the time and reducing the cost of producing a partition manager.

Logical partition manager and method

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Rochester, MN, United States of America

Michael Joseph Corrigan