Seagate Technology Incorporated

Michael Jon Roe

Brett Robert Herdendorf

Ronald Eldon Anderson

Justin Holwell

Michael Steven Quam

Andrew Michael Blair

Timothy A Madsen

Steven Ivars Palks

Dale Allen Blomgren

A method for forming an electrical connection with head gimbal assembly. At least a portion of an unmounted head gimbal assembly is placed on a surface. The unmounted head gimbal assembly includes a flexible portion, the flexible portion includes contact pads, and the surface includes electrical contacts and slots. A section of the flexible portion is pushed against the surface, and the contact pads are interconnected with the electrical contacts using a clamp assembly controlled by a computer. The clamp assembly includes a clamp with pins, and the interconnecting includes engaging the pins with the slots, rotating the clamp towards the surface, and clamping the contact pads against the electrical contacts.

Electrical connection for testing head gimbal assemblies

An assembly comprises a flex circuit including a first set of electrical contacts on a first side of the flex circuit and a compliant support backing adjacent a second side of the flex circuit and opposite the set of electrical contacts. The first set of electrical contacts is configured to connect to a second set of electrical contacts on an electronic component. The compliant support backing includes a set of support elements that individually support the first set of electrical contacts to increase the contact pressure between the first set of electrical contacts and the second set of electrical contacts when the flex circuit is connected to the electronic component. Embodiments may provide robust electrical contracts which provide a reliable connection useful for testing electronic components, such as head gimbal assemblies.

Electrical contacts with compliant supports

A method of optimizing write current in a data storage system. The write current is optimized by measuring a bit error rate in the storage system as a function of the write current in the presence of background interference stress and adjacent track interference stress. An optimum write current level is determined as a function of the measured bit error rate.

Performance based write current optimization process

Growing community of inventors

Becker, MN, United States of America

Michael Jon Roe