Alcatel

Trw Limited

Alcatel Internetworking, Inc.

Xylan Corporation

Michael Jon Nishimura

John Daniel Wallner

Michael K Wilson

Chris L Hoogenboom

John W Bailey

Todd Khacherian

Christopher Leo Hoogenboom

Todd L Khacherian

Henry E Huey

An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.

ATM switch with rate-limiting congestion control

A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from 'empty' to 'not empty', or vice versa, rather than on a &#x201c;per cell&#x201d; request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from &#x201c;not clear to release&#x201d; to &#x201c;clear to release&#x201d;, or vice versa, rather than on a &#x201c;per cell&#x201d; grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &#x201c;empty&#x201d; and the opposite binary value when the logical output queue's status is &#x201c;not empty&#x201d;. The status of each logical output queue is monitored at inputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &#x201c;not clear to release&#x201d; and the opposite binary value when the logical output queue's status is &#x201c;clear to release&#x201d;. Outputs generate (but do not transmit) release grants in a logical order determined by running a grant generation algorithm. Inputs release discrete information units in a logical order determined by running a release algorithm. Status messages for logical output queues are re-transmitted when extra bandwidth is available to remove any inaccurate view of the status of the logical output queues resulting from transmission failures of the original status messages.

Input buffering and queue status-based output control for a digital traffic switch

The present invention, generally speaking, uses input buffering and output control to provide a high-speed, high-performance digital traffic switch. This approach solves all of the problems noted above with respect to the prior art (input buffering/input control, output buffering/output control). Dropped discrete information units (cells) are dropped at the input port, and so will not be transmitted across the switch fabric. This reduces the traffic load on the switch fabric during congested periods, and makes the switch fabric easier to design and expand. Input buffering/output control allows for the use of smaller buffers than output buffered/output control architectures for the same level of &ldquo;discrete information unit (cell) drop&rdquo; performance, and scales well to larger systems. Input buffering/output control provides all the information necessary to the output (data flow) controller necessary to implement very precise control algorithms. These algorithms can then administer switch fabric admission polices and contract enforcement fairly across all input ports.

Input buffering/output control for a digital traffic switch

A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from &ldquo;empty&rdquo; to &ldquo;not empty&rdquo;, or vice versa, rather than on a &ldquo;per cell&rdquo; request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from &ldquo;not clear to release&rdquo; to &ldquo;clear to release&rdquo;, or vice versa, rather than on a &ldquo;per cell&rdquo; grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &ldquo;empty&rdquo; and the opposite binary value when the logical output queue's status is &ldquo;not empty&rdquo;. The status of each logical output queue is monitored at inputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &ldquo;not clear to release&rdquo; and the opposite binary value when the logical output queue's status is &ldquo;clear to release&rdquo;. Outputs generate (but do not transmit) release grants in a logical order determined by running a grant generation algorithm. Inputs release discrete information units in a logical order determined by running a release algorithm. Status messages for logical output queues are re-transmitted when extra bandwidth is available to remove any inaccurate view of the status of the logical output queues resulting from transmission failures of the original status messages.

The present invention, generally speaking, uses input buffering and output control to provide a high-speed, high-performance digital traffic switch. Dropped discrete information units (cells) are dropped at the input port, and so will not be transmitted across the switch fabric. This reduces the traffic load on the switch fabric during congested periods, and makes the switch fabric easier to design and expand. Input buffering/output control allows for the use of smaller buffers than output buffered/output control architectures for the same level of 'discrete information unit (cell) drop' performance, and scales well to larger systems. Input buffering/output control provides all the information necessary to the output (data flow) controller necessary to implement very precise control algorithms. These algorithms can then administer switch fabric admission polices and contract enforcement fairly across all input ports.

An improved address handling circuit includes a temporary storage device for temporarily storing at least one current cell, including a header, for address processing. A virtual channel (VC) filter is coupled to the temporary storage device and includes a VC address storage device for storing at least one selected virtual channel identifier (VCI), corresponding VC matching data and a corresponding cell identifier. The VC filter compares data from the header of the at least one current cell with the selected VCI to identify cells matching the at least one VCI. The VC filter includes a VC matching device for indicating a match. A virtual path (VP) filter is coupled to the temporary storage device and includes a VP address storage device for storing at least one selected virtual path identifier (VPI), corresponding VP matching data and a corresponding cell identifier. The VP filter compares the data from the header of the at least one current cell with the selected VPI to identify cells matching the at least one VPI. The VP filter includes a VP matching device for indicating a match. The VP filter has lower priority than said VC filter. A match priority device, coupled to the VC matching device of the VC filter and to the VP matching device of the VP filters, retrieves the matching data from a highest priority filter having a match.

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Torrance, CA, United States of America

Michael Jon Nishimura