Texas Instruments Corporation

3 Com Corporation

Michael John Zroka

Sri Navaneethakrishnan Easwaran

Ted F Lekan

Darren J Rollman

Srinath Mathur Ramaswamy

Lei Ding

Anand Gopalan

Ronald Joseph Sullivan

Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.

PS15 base current sampling in synchronous mode

Ultrasonic sensing systems and associated methods provide side-lobe reduction to improve the acoustic detection of small objects, the signature envelope peaks of which can otherwise be obscured by subsidiary envelope peaks in side lobes that result from residual correlation between a signal received by an ultrasonic transducer and a template signal corresponding to a burst signal emitted by the ultrasonic transducer. A shaping signal by which the amplitude of the burst signal can be varied with respect to time is taken into account in the template signal, and correlator circuitry correlates a signal derived from the ultrasonic transducer with the template signal to produce a correlated output exhibiting the desired side-lobe reduction. The distance from the transducer to the detected object can thereby be determined with enhanced accuracy and responsiveness.

Shaped ultrasonic transmission and echo processing with coding

PSI5 base current sampling in synchronous mode

A behavioral language-based methodology for the verification and testing of digital circuit designs. An automated or interactive simulation verification system can be used in accordance with the methodology to verify a digital circuit on inexpensive, simple digital circuit simulators, using behavioral languages, and achieve certain performance features found only on more costly, complex simulators.

Behavioral language models for testing and verification of digital

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Marengo, IL, United States of America

Michael John Zroka