Memc Electronic Materials, Inc.

Sunedison Semiconductor Limited

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Michael John Ries

Jeffrey Louis Libbert

Dale A Witte

Robert Wendell Standley

Charles Robert Lottes

Andrew Marquis Jones

Lance G Hellwig

Gregory M Wilson

Charles Chiun-Chieh Yang

Thomas A Torack

Jon A Rossi

Anca Stefanescu

Tom Torack

Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.

Methods for preparing layered semiconductor structures

A method of preparing a monocrystalline donor substrate, the method comprising (a) implanting helium ions through the front surface of the monocrystalline donor substrate to an average depth Das measured from the front surface toward the central plane; (b) implanting hydrogen ions through the front surface of the monocrystalline donor substrate to an average depth Das measured from the front surface toward the central plane; and (c) annealing the monocrystalline donor substrate at a temperature sufficient to form a cleave plane in the monocrystalline donor substrate. The average depth Dand the average depth Dare within about 1000 angstroms.

Method for low temperature layer transfer in the preparation of multilayer semiconductor devices

Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.

Methods for in-situ passivation of silicon-on-insulator wafers

Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.

Systems and methods for cleaving a bonded wafer pair

A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.

Epitaxial silicon wafer free from autodoping and backside halo and a method and apparatus for the preparation thereof

A holder for holding a semiconductor wafer for treatment in wafer treating apparatus including a plurality of supports for generally point support of the wafer at a plurality of points on the wafer. Each support bears a fraction of weight of the wafer and is movable up and down and subject to force biasing it to move upward. The total of the forces exerted on the supports biasing them upward is adapted to counterbalance the weight of the wafer.

Semiconductor wafer holder

An apparatus and method are provided for forming a denuded zone and an epitaxial layer on a semiconductor wafer used in manufacturing electronic components. The denuded zone and epitaxial layer are formed in one chamber. The apparatus includes a plurality of upstanding pins immovably mounted on a susceptor and maintain a semiconductor wafer spaced from the susceptor during both application of the epitaxial layer and formation of the denuded zone. Fast cooling of the wafer is accomplished by having the wafer out of conductive heat transfer relation with the susceptor during cooling thereof.

Method and apparatus for forming an epitaxial silicon wafer with a denuded zone

A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber. The system comprises a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber. The system also includes a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage. The bypass valve has an open position in which gas is permitted to flow through the bypass passage to equalize pressure between the process chamber and the wafer handling chamber and a closed position in which gas is prevented from flowing through the bypass passage to isolate the process chamber from the wafer handling chamber. In addition, the system includes a flow restrictor positioned along the bypass passage for restricting gas flow through the bypass passage to limit pressure change rates in the process chamber and the wafer handling chamber when the bypass valve is in the open position and thereby to limit a maximum velocity of gas flowing through the bypass passage.

Pressure equalization system for chemical vapor deposition reactors

A horizontal reactor for depositing an epitaxial layer on a semiconductor wafer. The reactor includes a reaction chamber sized and shaped for receiving the semiconductor wafer and a susceptor having an outer edge and a generally planar wafer receiving surface positioned in the reaction chamber for supporting the semiconductor wafer. In addition, the reactor includes a heating array positioned outside the reaction chamber including a plurality of heat lamps and a primary reflector for directing thermal radiation emitted by the heat lamps toward the susceptor to heat the semiconductor wafer and susceptor. Further, the reactor includes a secondary edge reflector having a specular surface positioned beside the heating array for recovering misdirected thermal radiation directed generally to a side of the heating array and away from the susceptor. The secondary edge reflector is shaped and arranged with respect to the heating array and the susceptor for re-directing the misdirected thermal radiation to the outer edge of the susceptor. Thus, the secondary edge reflector heats the edge and reduces thermal gradients across the susceptor and the semiconductor wafer to inhibit slip dislocations in the wafer during epitaxial layer deposition.

Growing community of inventors

St. Charles, MO, United States of America

Michael John Ries