International Business Machines Corporation

Michael John Palmer

Kelvin Wong

Michael T Benhase

Andrew Dale Walls

William Garrett Verdoorn, Jr

Bitwoded Okbay

Jianwei Zhuang

Ailoan Tran

Daniel Frank Moertl

Ian David Judd

Philip J Murfet

Christopher N Wallis

Gerald Mark Grabowski

Peter M Smith

Adrian C Lee

Thomas Winlow

Mandy Alexander Gray

Stephen Furniss

A method for improving performance of a host bus adapter in a data storage system is disclosed. In one embodiment, such a method uses, as an interface to a memory controller contained within a host bus adapter, multiple two-way ports configured to operate in parallel. The method uses, within each two-way port, a read FIFO buffer for transferring read data across the two-way port and a write FIFO buffer for transferring write data across the two-way port. The method also uses the read FIFO buffer and the write FIFO buffer within each two-way port to provide speed-matching for different clock speeds that operate on opposite sides of the two-way port. A corresponding system and computer program product are also disclosed.

High bandwidth SDRAM controller

There is a method and a corresponding system for performing partial write operations to memory. This method and corresponding system utilizes an XOR operation to generate error checking bits. Once the error checking bits are generated, they are then used for error checking a set of data bits so that these data bits can be written to memory.

Utilizing a link interface for performing partial write operations to memory

A method for improving performance of a direct memory access (DMA) transfer is disclosed. The method generates a descriptor that describes parameters of a DMA transfer to be performed by a DMA engine, such as a DMA engine within a host bus adapter of a data storage system. The method provides, in the descriptor, a field that describes an operation to be performed by the DMA engine. The field has as options an echo read operation, a dual write operation, a loop DDs operation, and a normal DMA transfer operation. The method provides the descriptor to the DMA engine. The DMA engine extracts the operation from the field and performs the operation. This operation may, in certain embodiments, move data through a host bus adapter of a data storage system. A corresponding system and computer program product are also disclosed.

High performance DMA transfers in host bus adapters

A mechanism is provided for loading a phase-locked loop (PLL) configuration into a PLL module using Flash memory. A Flash data image configuration from the Flash memory is loaded into a set of holding registers in response to the PLL module locking a current PLL configuration from a set of current configuration registers. The Flash data image configuration in the set of holding registers is compared to the current PLL configuration in the set of current configuration registers in response to the Flash data image configuration failing to be corrupted. The Flash data image configuration onto a PLL module input in response to the Flash data image configuration differing from the current PLL configuration. The Flash data image configuration is loaded in the set of holding registers into the set of current configuration registers in response to the PLL module locking the Flash data image configuration.

Loading a phase-locked loop (PLL) configuration using flash memory

A method, system, and computer program product are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command If a grown bad block is encountered whilst saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

Back-up and restoration of data between volatile and flash memory

A method and system are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command. If a grown bad block is encountered whilst saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

A logic circuit comprises a plurality of functional logic units each having an independent clock signal and a trace bus for carrying trace data. A trace gathering logic unit collects trace data from the functional logic units, the trace gathering logic unit having a clock signal independent of the clock signals of the functional logic units and a trace bus for receiving trace data from the functional logic units; multiplexing logic for multiplexing portions of trace data from different functional logic units onto the trace bus of the trace gathering logic unit; and, synchronization logic coupled to the multiplexing logic for communicating trace data from the functional, logic units to the trace gathering logic unit based on the clock signal of the trace gathering logic unit, the synchronization logic comprising detection logic when valid trace data from the functional logic units is available for placing on the trace bus of the trace gathering logic unit, and signaling logic coupled to the detection logic for signaling to the trace gathering logic unit that valid trace data is on the trace bus.

Logic circuit for the gathering of trace data

A method and system are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command. If a grown bad block is encountered while saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

In one embodiment, a method for back-up of data to flash memory is provided. Backed up data is organized into one or more stripes, wherein a stripe comprises a set of pages across all available flash memory devices which have a same block and page address. Responsive to encountering an error in a block of flash memory during back-up of a particular stripe of data, the particular stripe of data is rewritten starting at a next available page address and excluding a page of flash memory for the block having the error. Subsequent stripes of data in the block having the error are written to pages excluding the page of flash memory for the block having the error.

Back-up of data to flash memory. Data to back up is written into stripes, which are sets of pages across flash memory backup devices having the same block and page address. First metadata is embedded in each stripe indicating any blocks of the flash memory known to be bad. In response to encountering a new error in a block of flash memory during writing data to back up to a stripe, re-writing the stripe starting at the next available stripe excluding pages on the block of flash memory having the new error, writing subsequent stripes excluding pages on the block of flash memory having the new error, and embedding second metadata in the re-written and subsequent stripes indicating the location of the block having the new error. Responsive to finding no bad blocks indicated in the first metadata, initiating a write to two or more stripes simultaneously.

Fast data back-up and restore between volatile and flash memory

An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.

Apparatus, system, and method for mandatory end to end integrity checking in a storage system

An apparatus, system, and method are disclosed for data error checking and recovery in a data storage device. A redundancy check module creates a redundancy check for data on a data storage device in a SCSI End-to-End Checking Standard environment and a redundancy check storage module stores the redundancy check in a guard associated with the data.

Apparatus, system, and method for error checking and recovery of transmitted data in a SCSI environment

The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.

VLSI chip macro interface

Channel selection arbitration

An asynchronous serial data receiver for receiving a stream of data bits, characterized by a plurality of shift registers (54) into which samples corresponding to points within said data bit stream are read, different shift registers (54) holding a different set of said samples, said points being separated by most one half of a data bit period, and a decoder (60-90) responsive to said samples held in said shift registers (54) for recognizing points of known phase within said data assessed relative to which samples which corresponding to points within said data bits may be identified for reading. The invention provides a high speed serial receiver which is particularly suitable for use within disc drives and data storage and retrieval systems in general. The serial data receiver of the present invention does not require a clock synchronized with the incoming data. Furthermore the serial data receiver is able to share the sampling of the data bit stream between a plurality of shift registers (54) none of which need be clock more than once per data bit period.

Growing community of inventors

Southampton, United Kingdom

Michael John Palmer