International Business Machines Corporation

Michael John Mayfield

David Scott Ray

Dwain Alan Hicks

Francis Patrick O'Connell

Robert J Reese

Shih-Hsiung Stephen Tung

Peichun Peter Liu

Michael Thomas Vaden

Kin Shing Chan

James Allan Kahle

Edward John Silha

Trinh Huy Nguyen

Kevin Arthur Chiarot

Joel M Tendler

Peter Steven Lenk

Milford John Peterson

Era Kasturia Nangia

Michael T Benhase

James Stephen Fields, Jr

Bruce Gerard Mealey

Brian David Barrick

Robert Alan Cargnoni

Sanjay Raghunath Deshpande

Alvan Wing Ng

Rajinder Paul Singh

Brian Patrick Hanley

George A Lerom

Dwight A Gourneau

James W Allen

Lisa Graybeal

Scott W Hinkel

Michael R Crabtree

Charles S Burns

Three part skillet

Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.

Method, system, and program for transferring data directed to virtual memory addresses to a device memory

An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

Fixed snoop response time for source-clocked multiprocessor busses

In a multiprocessor system using snooping protocols, system command conflicts are prevented by comparing processor commands with prior snoops within a specified time defined window. A determination is then made as to whether a command issued by a given processor is likely to cause a system conflict with another command issued within said specified time defined window. If so, the time of execution of any such snoop command determined as being likely to cause a system conflict is delayed. This approach uses address bus arbitration rules to prevent system livelocks due to both coherency and resource conflicts.

Method and apparatus for livelock prevention in a multiprocessor system

A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

Method and apparatus for mapping software prefetch instructions to hardware prefetch logic

A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks. In another implementation, the master devices use a bus protocol that prevents Read-Read deadlocks in a distributed, multi-bus, multiprocessor system.

Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock

A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.

Programmable data prefetch pacing

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

Software prefetch system and method for predetermining amount of streamed data

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

System and method for prefetching data using a hardware prefetch mechanism

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

Cache prefetching of L2 and L3

A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access. The first and second cache accesses preferably occur in consecutive cycles. Typically, the first and second operations are store operations that are queued in the stack in program order. In one embodiment the first operation is removed from the stack upon resolving of the resource conflict.

Efficient store machine in cache based microprocessor

A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit. This deallocation of the first line of the cache memory occurs regardless of a completion status of the bus interface unit transfer whereby a pending fill of the first cache line may proceed prior to completion of the bus interface unit transfer. In one embodiment, the storeback buffer includes first and second segments for storing first and second segment data respectively. In this embodiment, the deallocation pipelining circuit is able to detect the completion of the transfer of the first segment data during the bus interface unit transfer and preferably configured to initiate an SBB transfer of second line data from a second line in the cache memory array in response to the completion of the first segment data transfer. In this manner, the initiation of the second line SBB transfer precedes the completion of the first line bus interface unit transfer.

Pipelined cache memory deallocation and storeback

An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during testing of the pre-fetching stream hits. Therefore, the two Effective Address (EA) accesses and a RCAM snoop access can access the data cache simultaneously thereby increasing pre-fetching performance.

Method and system for pre-fetch cache interrogation using snoop port

In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

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Austin, TX, United States of America

Michael John Mayfield