Seagate Technology Incorporated

Medtronic, Inc.

Michael John Link

Bruce Douglas Buch

William Michael Radich

Jason Charles Jury

Belkacem Derras

Jason Bellorado

Ara Patapoutian

Marcus Marrow

Guofang Xu

Kinhing Paul Tsang

David K Peterson

Richard P Michel

Anand R Kharpate

Systems, devices, and method for phase slip recovery may include reading a plurality of data portions of a data block and positioning a mask over one or more data portions of the data block. The data portions following the mask may be shifted to provide a masked, reframed data block, and then the data block may be attempted to be decoded, which may be repeated until the data block is decoded.

Phase slip recovery

An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.

MISO equalization with ADC averaging

A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Self-adapting phase-locked loop filter for use in a read channel of a heat assisted magnetic recording drive

A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

Phase error recovery circuitry and method for a magnetic recording device

Self-adapting phase-locked loop filter for use in a read channel

Multiple signals are read, respectively, from multiple different cross-track positions of a track of a magnetic medium. Weighting coefficients for each of the multiple signals are determined. The weighting coefficients are applied to the respective signals to form weighted signals. The weighted signals are combined and the combined signal is used to recover data stored in the track.

Noise cancellation using cross-track scans

Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.

Reduced state soft output processing

A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint, wherein at least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.

High rate running digital sum-restricted code

A cardiac stimulator and a method of its use. The stimulator includes a lead system carrying a stimulation electrodes adapted to be located at multiple sites adjacent tissue of a patient's heart and is provided with stimulation pulse generators coupled to deliver stimulation pulses to the stimulation electrodes. The stimulator further includes depolarization sensors responsive to depolarizations of cardiac tissues at the tissue sites and, responsive to sensed depolarizations and stimulation pulses delivered to said sites by said stimulation electrodes determines exitable gaps of tissue at the sites. The stimulator calculates stimulus pulse delivery times at variable delivery times within the determined exitable gaps at the tissue sites to cause convergence of depolarization cycles at the tissue sites over a series of delivered stimulation pulses and delivers stimulation pulses to the stimulation electrodes at the calculated variable delivery times.

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Saint Paul, MN, United States of America

Michael John Link