International Business Machines Corporation

Globalfoundries Inc.

Michael John Hamilton

Steven Michael Douskey

Amanda Renee Kaufer

Ryan Andrew Fitch

Phillip A Senum

Mary Prilotski Kusko

Matthew B Schallhorn

Brandon Edward Schenck

Norman Karl James

Jason T Albert

Dennis Martin Rickert

Timothy J Eby

James Fred Daily

William T Bronk

A method and circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test due to Channel Mask Enable (CME) sharing, and a design structure on which the subject circuit resides. A common Channel Mask Scan Registers (CMSR) logic is used with a multiple input signature register (MISR). Individual local addressing is used for implementing enhanced scan data testing. An architecture and algorithm efficiently expand and target the use of the CME pins to minimize over-masking, to increase test pattern effectiveness with the use of individual local addressing.

Minimization of over-masking in an on product multiple input signature register (OPMISR)

A method and circuit for implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG), and a design structure on which the subject circuit resides are provided. A random fault is selected in the design. A test pattern is generated and applied the test pattern to a design under test to test the selected random fault. The test is re-simulated to determine faults that are covered by the applied test pattern. A next iteration of test pattern generation includes selecting a fault that is based upon the previous test pattern generation for generating new test patterns.

Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

A method and test circuit are provided for implementing enhanced scan data testing with removal of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing to allow sharing the CMSR data and common Channel Mask Enable (CME) pins with removal of over masking. Selectively pausing scan unload is provided for each respective satellite when wrong CME data for the respective satellite is at the CME pins. Each satellite includes a select signal which controls advancing the scan into the MISR. The select signal is used to selectively pause the scan unload for the respective satellite.

Removal of over-masking in an on product multiple input signature register (OPMISR) test

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing

A method and circuit are provided for implementing enhanced scan data testing with over masking removal in an on product multiple input signature register plus (OPMISR+) test due to common Channel Mask Scan Registers (CMSRs) loading, and a design structure on which the subject circuit resides. An OPMISR plus satellite includes a multiple input signature register (MISR) for data collection and a plurality of associated scan channels. A common Channel Mask Scan Registers (CMSR) logic is used with the multiple input signature register (MISR). Unique CMSR data is loaded into at least one OPMISR plus satellite for implementing enhanced scan data testing. Scan pausing is used to reduce the amount of CMSR scan load data by loading the unique CMSR data only when needed.

Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

Implementing register array (RA) repair using LBIST

A method and circuits are provided for implementing enhanced scan data testing using an XOR network to prioritize faults to be simulated during diagnostic isolation, and reducing the number of faults requiring re-simulation. A test is run, scan data are applied to scan channels using the XOR network and the output scan data are unloaded. A list of possible faults is identified based on pin flips, and the possible faults to be simulated during diagnostic isolation are prioritized by a number of occurrences in the list, and possible faults are further graded to reduce the number of possible faults requiring re-simulation.

Implementing prioritized compressed failure defects for efficient scan diagnostics

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in On Product Multiple Input Signature Register (OPMISR) testing through spreading in a stump mux data chain structure, and a design structure on which the subject circuit resides are provided. The stump mux chain structure includes a plurality of stump muxes connected in series by a respective rotation function. A respective exclusive OR (XOR) spreading function included with each of the plurality of stump muxes provides channel inputs. XOR inputs are applied to each XOR spreading function providing unique input combinations for each respective channel included with each of said plurality of stump muxes. The respective rotation function enables test data to be rotated as scan data enters each stump mux to further make the test data unique for each stump mux.

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure

A method and circuit are provided for implementing enhanced scan data testing for test time reduction and decreased scan data interdependence with on product multiple input signature register (OPMISR++) testing, and a design structure on which the subject circuit resides. A respective Pseudo-Random Pattern Generator (PRPG) provides channel input patterns to a respective associated scan channel used for the OPMISR++ diagnostics. Control inputs are coupled to the Pseudo-Random Pattern Generator (PRPG) providing PRPG control distribution. The PRPG selectively provides controlled channel input patterns for the respective scan channel responsive to the control inputs.

Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation

An IO structure, method, and apparatus are disclosed for using an IEEE&#x2122; 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE&#x2122; 1149.1 boundary scan latches may include using the IEEE&#x2122; 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE&#x2122; 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

Managing redundancy repair using boundary scans

A method and apparatus are provided for isolating a defect in a scan chain comprising a plurality of components of an integrated circuit. A plurality of injection points may be positioned along the scan chain. Each injection point may be configured to introduce binary test data. A plurality of bypass structures may each be configured to selectively direct a flow of the binary test data to generate a plurality of partitioned scan paths. Test logic may be configured to execute a plurality of tests using the plurality of partitioned scan paths and to combine results of the plurality of tests to isolate a faulty component of the plurality of components.

Partitioned scan chain diagnostics using multiple bypass structures and injection points

A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

Inserting bypass structures at tap points to reduce latch dependency during scan testing

A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

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Rochester, MN, United States of America

Michael John Hamilton