Mayo Foundation for Medical Education and Research

Xilinx, Inc.

Michael John Degerstrom

Matthew L Bibee

Barry K Gilbert

Erik S Daniel

Patrick Joseph Zabinski

Christopher Keith White

Jonathan L Fasig

Daniel V Hulse

Chad M Smutzer

A technique for non-invasively assessing current drawn by a device under test (DUT) by monitoring a supply voltage to the DUT. Frequency data for the DUT may be generated and used to form a current estimation model. First and second voltages are simultaneously measured using first and second test probes electrically connected to the DUT, while the first test probe is connected at a current source, and while the second test probe is connected at a DUT load that is configured to draw current from the current source. The current drawn by the DUT is then assessed by applying the current estimation model to the measured first and second voltages. In one case, the current drawn by the DUT is estimated without insertion of a circuit component into the DUT or extraction of a circuit conductor from the DUT.

Systems and methods for non-invasive current estimation

Application of open and short structures may result in improved accuracy in determination of ABCD parameters of a substantially symmetric two-port network for purposes of bisect de-embedding. Either one or both of the open and/or short techniques may be used to improve results of an ABCD optimization algorithm. Bisect de-embedding may then be performed to determine the ABCD parameters of a device under test based on the ABCD parameters of the substantially symmetric two-port network and measured s-parameters of the substantially symmetric two-port network and the embedded device under test.

Application of open and/or short structures to bisect de-embedding

Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Next, all commonly defined port definitions are combined into a single port definition. Finally, a current analysis is used to further reduce the number of port definitions in the simulation file by removing the current return ports from the simulation file.

Apparatus and method for port reduction in simulation files

A printed circuit board (PCB) embedded filter is utilized to provide a low-pass filter characteristic using minimal lumped circuit elements. Microstrips extend on top layer of the PCB to conductive vias to form a first series connected inductive element, while microstrips extend from conductive vias to conductive vias to form a second series connected inductive element. Shunt capacitance is employed on a lower layer using striplines extending outwardly and symmetrically from conductive vias. An absorption circuit is implemented using microstrips on back layer of the PCB and capacitive plates on inner layers of the PCB. A surface mount resistor may be installed between pads to complete the absorption circuit.

Method and apparatus for a printed circuit board (PCB) embedded filter

Various apparatus for performing high frequency electronic package testing are disclosed. A test fixture assembly includes an electronics package having an interface structure, a mock-up IC, coupled to the interface structure for providing circuit connections, and a fixture board, coupled to the interface structure, wherein at least one of the fixture board and mock-up IC includes high frequency probe pads for providing a signal and ground point for high bandwidth test probing. Raw measurements are used for validation of the electronic package specifications when adequate test fixture bandwidth is available or included into circuit simulations models when a minimal phase error is acceptable, else phase and loss corrections are applied to the measurements.

Apparatus for performing high frequency electronic package testing

A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal. A multiplexer circuit coupled to each data signal delay and sampling circuit and to the comparator and decision circuit outputs the selected time-slice bit sample of each word bit of the parallel data signal as the phase-aligned parallel data signal. A first-bit intialization circuit connected to the clock terminal and the data ready terminal and coupled to the multiplexer causes the time-slice bit samples corresponding in time to the logic state transition of the data ready signal to be outputted as a first one or more information bits of the phase-aligned data signal before the comparator and decision circuit operates to compare and select one of the plurality of time-slice bit samples.

Data bit-to-clock alignment circuit with first bit capture capability

A self-terminating FET digital logic receiver for impedance-matched interconnection to a transmission line having a uniform characteristic impedance. The receiver includes an input terminal, a current mirror formed by first and second FETs, and a load. First and second non-zero current level digital logic signals are received from the transmission line at the input terminal. The first current mirror FET is connected to the input terminal and configured to provide nonlinear current/voltage characteristics between the first and second current levels which approximate the characteristic impedance of the transmission line. Substantially all the current of the digital logic signals is therefore absorbed by the first FET to minimize signal reflections on the transmission line. The second FET is connected to the first FET to provide a mirror current having current levels proportional to the current levels of the digital logic signals. The load is connected to the second FET of the current mirror, and produces voltage level signals representative of the digital logic signals.

Growing community of inventors

Rochester, MN, United States of America

Michael John Degerstrom