Advanced Micro Devices Corporation

Michael John Bedy

Robert A Gottlieb

Christopher L Reeve

Steven Tony Tye

Anton Chernoff

Guohua Jin

Nicolai Haehnle

Alex Shye

Eric J Finger

Mark Herdeg

Richard L Ford

An apparatus and method for efficiently scheduling wavefronts for execution on an integrated circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple, replicated compute circuits. Each compute circuit executes one or more wavefronts. Each compute circuit includes a cache configured to store temporary data that cannot fit in the vector general-purpose register file of the compute circuit. Each wavefront requests a corresponding amount of storage space in the cache for storing the temporary data. When the available data storage space in the cache is less than a data size requested by a wavefront waiting to be dispatched, a control circuit of the compute circuit reduces a dispatch rate of wavefronts. The control circuit also reduces an issue rate of instructions of one or more dispatched wavefronts to assigned execution circuits of the compute circuit.

Dynamic accounting of cache for GPU scratch memory usage

A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

System and method for scheduling instructions in a multithread SIMD architecture with a fixed number of registers

Described herein are techniques for saving registers in the event of a function call. The techniques include modifying a program including a block of code designated as a calling code that calls a function. The modifying includes modifying the calling code to set a register usage mask indicating which registers are in use at the time of the function call. The modifying also includes modifying the function to combine the information of the register usage mask with information indicating registers used by the function to generate registers to be saved and save the registers to be saved.

Register saving for function calling

A method and apparatus provides for compiling a plurality of shaders, each shader having a plurality of computer-readable statements, into a plurality of computer-executable instructions. In one example, the method and apparatus, using a computing device, receives the plurality of shaders used in a process pipeline for performing at least one shading function, determines a shader type of each of the plurality of shaders based on the at least one shading function, and compiles the plurality of shaders by generating the computer-executable instructions using data including a shader descriptor for each of the plurality of shaders, resulting in the shading functions of the plurality of shaders combined together.

Method and apparatus of cross shader compilation

A method of deriving intended thread data exchange patterns from source code includes identifying, based on a constant array, a pattern of data exchange between a plurality of threads in a wavefront. The constant array includes an array of source lane values identifying a thread location within the wavefront to read from for performing the pattern of data exchange. The pattern of data exchange is identified as a hardware-accelerated exchange pattern based on the constant array.

Flexibly deriving intended thread data exchange patterns

A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.

Lightweight service based dynamic binary rewriter framework

An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a larger scope for transformation (e.g. optimization) than traces. Hardware samples are used to identify SRs that contain the hot code of a client process without requiring any static program information.

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Boxborough, MA, United States of America

Michael John Bedy