Alcatel

Alcatel N.v.

Other

Alcatel Lucent

Alcatel Alsthom Compagnie Generale D'electricite

Michael Joachim Wolf

Werner Beisel

Geoffrey Dive

Dieter Beller

Henry W Owen

J&uuml;rgen Kasper

J&uuml;rgen H&ouml;hn

Chris B Autry

Wolfgang Thiele

Helmut Brunner

A crossconnect for asynchronous OTN signals operates synchronously internally at an internal clock rate. Received OTN signals are synchronized to an internal frame format by stuffing. The synchronized signals are parallelized and switched with a switching matrix comprising synchronously operating integrated circuits that operate at the internal clock rate. At the output, the synchronized signals are again destuffed and are transmitted again at the original bit rate.

Network element for signals of the optical transport network (OTN)

A clock filter circuit (), which serves for filtering the clock of non-isochronous data signals having a selected one of at least two nominal data rates, has an auxiliary clock source () that generates an auxiliary clock signal () with a pulse repetition rate which is in the range between the at least two predetermined data rates, a delay line () connected to the auxiliary clock source () for creating a set of mutually delayed copies of the auxiliary clock signal and a multiplexer () that switches in a cyclic order between the delayed copies according to predetermined rules, which depend on the selected data rate to generate a filtered clock signal (). A control circuit determines whether the rate of the filtered clock () signal must be increased or decreased as compared to said data signal and controls the multiplexer () to delay or advance the cyclical switching accordingly.

Digital clock filter circuit for a gapped clock of a non-isochronous data signal having a selected one of at least two nominal data rates

A burst mode optical signal is transported as payload of a framed continuous bit-stream optical signal through an optical transport network. The optical bursts are all generated at a common nominal bitrate which equals substantially the payload bitrate of the continuous bit-stream optical signal. The bursts are converted into a continuous bit stream by filling gaps between the bursts with a predefined pattern. The continuous bit stream thus created is then mapped into frames to generate the framed continuous bit-stream optical signal for transmission.

Optical packet transmission

A network element with equipment protection has first and second redundant signal paths for first and second redundant signals; a selector for selecting either of the two redundant signals as active; and first and second transition monitors coupled to the first and second signal paths, respectively, for monitoring the first and second signals for bit level transitions. The selector is controlled by the transition monitors to alter selection in the case that the selected signal does not contain bit level transitions while the non-selected signal does.

Hitless protection switching

A desynchronizer for extracting and desynchronizing a tributary signal from a multiplex signal at its original data rate has a buffer memory for temporarily storing tributary data bits extracted from the multiplex signal, an adjustable oscillator for generating a read clock for reading the tributary data bits or bytes from the buffer, and a comparator for comparing the read and write timing rates of the buffer memory in synchronism with the frame rate of the multiplex signal to generate a control signal to adjust the oscillator.

Plesiochronous demultiplexer

A network device (NWE) for a digital transmission network with synchronous digital hierarchy receives data steams containing frames with data packets mapped therein and addressed by a phase reference identifier. Internally, the network device has redundant transfer paths which potentially cause different delay. The network element compensates for that delay by adjusting the phase reference identifier allocated to a respective data packet by a predetermined phase correcting value, leading in the phase, which corresponds to a maximum expected delay for transfer of the data packets on internal transfer paths, and by buffering the data packet by a buffering time such that its buffering time and its delay actually needed for passing through the network device in total correspond to the maximum expected delay taken into account by the phase adjustment.

Network device and method for delay compensation of data packets

A method of synchronizing at least one receiver module (MOD , MOD ), in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, has the following steps: A first clock signal (TS ) and a second clock signal (TS ) are sent to the at least one receiver module (MOD , MOD ). In addition, at least one item of master-slave-status information (MSX) about the at least one first clock signal (TS ) and/or the second clock signal (TS ) is sent to the at least one receiver module (MOD , MOD ). Based on the item of master-slave-status information (MSX), the at least one receiver module (MOD , MOD ) selects the first clock signal (TS ) or the second clock signal (TS ) as master synchronization signal for its synchronization.

Method, clock generator module and receiver module for synchronizing a receiver module

The synchronous digital communications system according to the invention serves to transmit electric signals optically. The electric signals to be transmitted are converted from electrical to optical form (E/O E/O E/On) and then transmitted using wavelength division multiplexing (WDM) or dense wavelength division multiplexing (DWDM). A synchronization manager and a connection manager are provided. The synchronization manager is adapted to configure dedicated optical synchronization links. The connection manager is adapted to configure switched optical communication links from a pool of wavelengths, taking account of the dedicated synchronization links only. This has the advantage that independently of the switched communication links, synchronization is constantly ensured throughout the system. Each network element (NE , NE , NE ) has at least one interface unit that is reserved for synchronization and that continuously receives signals at the wavelength (&lgr; ) reserved for synchronization.

Synchronous digital communications system

The synchronous digital communications system according to the invention serves to transmit electric signals optically. The electric signals to be transmitted are converted from electrical to optical form (E/O E/O E/On) and are transmitted using wavelength division multiplexing (WDM) or dense wavelength division multiplexing (DWDM). At least one optical connection is configured as a nonswitched connection using at least one wavelength per transmission section between optical network elements or optical and electrical network elements, and serves to transmit synchronization and information signals. This has the advantage that independently of the switched communication links, synchronization is constantly ensured throughout the network. Each network element (NE NE NE ) has at least one interface unit that is reserved for synchronization and that continuously receives signals at the wavelength (&lgr; ) reserved for synchronization.

A method of transmitting clock signals (CS) in a synchronous digital communications network and a method of synchronizing clock generators (SSU) or network elements (SEC) wherein signaling of the clock quality is effected by phase-modulating the clock signal (CS). The clock signal (CS) is transmitted and received through simple clock interfaces (T , CLO; T , CLI) and contains a phase modulation characteristic of the clock quality. The phase modulation is detected and quality information is derived therefrom. Based on the quality information, the clock generator (SSU) or the network element (SEC) are synchronized to the clock signal. Also disclosed are a clock generator (SSU) and a network element (SEC; NE) for carrying out the two methods.

Method of transmitting clock signals, method of synchronizing clock generators or network elements, as well as a network element and a clock generator

A network element is provided for receiving receives message signals and reading the synchronization status messages contained therein. The network element transmits the message signals to a central network management facility which selects one of the message signals as a timing reference based on the synchronization status messages and based on stored information about the structure and configuration of the network. The network management facility then notifies the network element of the selection. The network element derives a clock signal from the selected message signal and uses this clock signal to adjust an internal clock generator. Because the network management facility also has information about parallel transmission paths, the creation of timing loops is effectively prevented.

Synchronization of a network element in a synchronous digital communications network

A switching device ( ) for an optical transmission network is provided with a first switch ( ) to which a plurality of fibers ( ) are attached, each of which fibers ( ) is provided with a plurality of channels ( ) with different wavelengths. The first switch ( ) is suitable for connecting each channel ( ) of each of the fibers ( ) to any other channel ( ) of the fibers ( ). At least one channel ( &prime;) of the fibers ( ) is not attached to the first switch ( ), but is instead attached to a second switch ( ). The second switch ( ) is in this case suitable only for connecting each channel ( &prime;) of a first of the fibers ( ) to each channel ( &prime;) of a second of the fibers ( ).

Switching device for an optical transmission network

A desynchonizer for a synchronous digital communications system serves to recover a useful signal from a synchronous digital input signal. It comprises a buffer for temporarily storing the input signal, a write circuit for writing the input signal into the buffer, a clock-generating circuit for generating a clock signal, and a read circuit for reading the contents of the buffer at the recovered clock rate. According to the invention, the clock-generating circuit includes a calculating circuit for determining an average over the interval between two pointer actions of the input signal, and derives from the average a tuning signal which serves to adjust the recovered clock signal. In this manner, jitter caused by pointer actions which result from a constant offset of the effective bit rate of the received virtual containers is eliminated.

Desynchronizer for a synchronous digital communications system

A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Growing community of inventors

Mundelsheim, Germany

Michael Joachim Wolf