International Business Machines Corporation

Other

Globalfoundries Inc.

Lam Research Corporation

Morton International, Inc.

Sienens Aktiengesellschaft

Michael Jay Shapiro

Louis Bennie Capps, Jr

Robert H Bell, Jr

Ronald Edward Newhart

Thomas Edward Cook

Anand Haridass

Michael A Paolini

Glenn Graham Daves

Edmund Juris Sprogis

Mario John Interrante

Warren D Dyckman

Son Van Nguyen

Sang Hoo Dhong

Luis Alfonso Lastras-Montano

Vincent James McGahay

Jean Audet

Brent William Yardley

Tae Hong Kim

Brian Chase Twichell

Van Thanh Truong

Daniel Mark Dreps

Naresh Nayar

John Anthony Fitzsimmons

Gary Dale Carpenter

Kevin John Nowka

James Gardner Ryan

Alan J Drake

Albert M Young

Sarah Huffsmith Knickerbocker

Ashima B Chakravarti

Michael F McAllister

Thomas W Mountsier

Mark Elliott Hack

Luc Gilbert Guerin

Steven Paul Hartman

Rachel Gordin

William F Van Duyne

Thuy L Tran-Quinn

Natalia Borjemscaia

Edward M DeMulder

Joanne Ferris

Anthony K Stamper

Huilong Zhu

John Ulrich Knickerbocker

Bing Dang

Bucknell Chapman Webb

Michael Richard Ouellette

Harm Peter Hofstee

Richard Anthony Conti

Christopher Joseph Waskiewicz

William Thomas Motsiff

Thomas Anthony Wassick

David M Dobuzinsky

Tetsuo Matsuda

William Elton Burky

David Hirsch Danovitch

Jonathan Daniel Chapple-Sokol

Bernadette Ann Pierson

Matthias Ilg

Thomas J Dewkett

Markus M Kirchhoff

Paul Marian Harvey

James Douglas Jordan

Dmitriy Shneyder

Gary Lafontant

Karen Lynne Holloway

Nickolaus J Gruendler

Sang Y Lee

Paul F Seidler

Ben C Hui

Srinivasan Rangarajan

Kevin A McKinley

Terry M Cheng

Ravi Kanjolia

Louis B Capps

Danie M Dreps

An error in content generated by a first electronic device can be detected by a second electronic device. The second electronic device receives, in one or more messages, first message content and second message content generated by integrated circuit logic within the first electronic device. The second electronic device compares the first message content with predetermined message content. Based on detecting a mismatch between the first message content and the predetermined message content, the second electronic device initiates error recovery for the one or more messages. Initiating error recovery can include, for example, logging an error in the integrated circuit logic, requesting for the first electronic device to regenerate the first message content and second message content, or initiating execution of a program that detects and corrects programming errors in the integrated circuit logic.

Detection of an error generated within an electronic device

According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.

System, method and computer program product for data transfer management

According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted to the processor unit instead of the requested data as a response to the read request, and the processor unit replaces the pattern tag with the corresponding data pattern.

An apparatus includes a particle trap coupled to a first surface of an enclosure, wherein the first surface of the enclosure is opposite a top surface of a circuit board. A particle guard coupled to the top surface on a first side of the circuit board located in the enclosure, wherein the enclosure includes one or more apertures on a second surface of the enclosure where the first side of the circuit board is introduced to an external airflow.

Dust guard structure

An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.

A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.

Multicore processor and method of use that configures core functions based on executing instructions

According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

Corrosion resistant chip sidewall connection with crackstop and hermetic seal

The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.

Electrical connection around a crackstop structure

A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

Stacked through-silicon via (TSV) transformer structure

A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

Coil inductor for on-chip or on-chip stack

Serializer-deserializer (SERDES) and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. The first and second SERDES dies positioned adjacent, in a plane, and disposed on the package substrate. The logic circuit communicatively connected to the SERDES circuit and to the package substrate. The logic die stacked vertically and disposed on the first and second SERDES dies. A method of assembling a SERDES and integrated circuit package including providing a SERDES structure selected from a menu of SERDES die and SERDES circuit combinations. A design structure of a SERDES and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate.

Structure for logic circuit and serializer-deserializer stack

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Austin, TX, United States of America

Michael Jay Shapiro