Intel Deutschland Gmbh

Tesa Se

Michael Janning

Axel G Huebner

Jens Berkmann

Nicolai Böhm

Andreas Hagemann

Domenico Boccuto

A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

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Mettmann, Germany

Michael Janning